/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018 Renesas Electronics Corp. * Copyright (C) 2018 Cogent Embedded, Inc. */ #ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ #include <dt-bindings/clock/renesas-cpg-mssr.h> /* r8a77980 CPG Core Clocks */ #define R8A77980_CLK_Z2 0 #define R8A77980_CLK_ZR 1 #define R8A77980_CLK_ZTR 2 #define R8A77980_CLK_ZTRD2 3 #define R8A77980_CLK_ZT 4 #define R8A77980_CLK_ZX 5 #define R8A77980_CLK_S0D1 6 #define R8A77980_CLK_S0D2 7 #define R8A77980_CLK_S0D3 8 #define R8A77980_CLK_S0D4 9 #define R8A77980_CLK_S0D6 10 #define R8A77980_CLK_S0D12 11 #define R8A77980_CLK_S0D24 12 #define R8A77980_CLK_S1D1 13 #define R8A77980_CLK_S1D2 14 #define R8A77980_CLK_S1D4 15 #define R8A77980_CLK_S2D1 16 #define R8A77980_CLK_S2D2 17 #define R8A77980_CLK_S2D4 18 #define R8A77980_CLK_S3D1 19 #define R8A77980_CLK_S3D2 20 #define R8A77980_CLK_S3D4 21 #define R8A77980_CLK_LB 22 #define R8A77980_CLK_CL 23 #define R8A77980_CLK_ZB3 24 #define R8A77980_CLK_ZB3D2 25 #define R8A77980_CLK_ZB3D4 26 #define R8A77980_CLK_SD0H 27 #define R8A77980_CLK_SD0 28 #define R8A77980_CLK_RPC 29 #define R8A77980_CLK_RPCD2 30 #define R8A77980_CLK_MSO 31 #define R8A77980_CLK_CANFD 32 #define R8A77980_CLK_CSI0 33 #define R8A77980_CLK_CP 34 #define R8A77980_CLK_CPEX 35 #define R8A77980_CLK_R 36 #define R8A77980_CLK_OSC 37 #endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| Sergei Shtylyov | 167 | 100.00% | 1 | 100.00% |
| Total | 167 | 100.00% | 1 | 100.00% |