Release 4.17 sound/soc/intel/skylake/skl.h

/*
 *  skl.h - HD Audio skylake defintions.
 *
 *  Copyright (C) 2015 Intel Corp
 *  Author: Jeeja KP <jeeja.kp@intel.com>
 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 */

#ifndef __SOUND_SOC_SKL_H

#define __SOUND_SOC_SKL_H

#include <sound/hda_register.h>
#include <sound/hdaudio_ext.h>
#include <sound/soc.h>
#include "skl-nhlt.h"
#include "skl-ssp-clk.h"


#define SKL_SUSPEND_DELAY 2000


#define SKL_MAX_ASTATE_CFG		3


#define AZX_PCIREG_PGCTL		0x44

#define AZX_PGCTL_LSRMD_MASK		(1 << 4)

#define AZX_PGCTL_ADSPPGD		BIT(2)

#define AZX_PCIREG_CGCTL		0x48

#define AZX_CGCTL_MISCBDCGE_MASK	(1 << 6)

#define AZX_CGCTL_ADSPDCGE		BIT(1)
/* D0I3C Register fields */

#define AZX_REG_VS_D0I3C_CIP      0x1 
/* Command in progress */

#define AZX_REG_VS_D0I3C_I3       0x4 
/* D0i3 enable */

#define SKL_MAX_DMACTRL_CFG	18

#define DMA_CLK_CONTROLS	1

#define DMA_TRANSMITION_START	2

#define DMA_TRANSMITION_STOP	3


#define AZX_REG_VS_EM2_L1SEN		BIT(13)


struct skl_dsp_resource {
	
u32 max_mcps;
	
u32 max_mem;
	
u32 mcps;
	
u32 mem;
};

struct skl_debug;


struct skl_astate_param {
	
u32 kcps;
	
u32 clk_src;
};


struct skl_astate_config {
	
u32 count;
	
struct skl_astate_param astate_table[0];
};


struct skl_fw_config {
	
struct skl_astate_config *astate_cfg;
};


struct skl {
	
struct hdac_ext_bus ebus;
	
struct pci_dev *pci;

	
unsigned int init_done:1; /* delayed init status */
	
struct platform_device *dmic_dev;
	
struct platform_device *i2s_dev;
	
struct platform_device *clk_dev;
	
struct snd_soc_component *component;
	
struct snd_soc_dai_driver *dais;

	
struct nhlt_acpi_table *nhlt; /* nhlt ptr */
	
struct skl_sst *skl_sst; /* sst skl ctx */

	
struct skl_dsp_resource resource;
	
struct list_head ppl_list;
	
struct list_head bind_list;

	
const char *fw_name;
	
char tplg_name[64];
	
unsigned short pci_id;
	
const struct firmware *tplg;

	
int supend_active;

	
struct work_struct probe_work;

	
struct skl_debug *debugfs;
	
u8 nr_modules;
	
struct skl_module **modules;
	
bool use_tplg_pcm;
	
struct skl_fw_config cfg;
	
struct snd_soc_acpi_mach *mach;
};


#define skl_to_ebus(s)	(&(s)->ebus)

#define ebus_to_skl(sbus) \
	container_of(sbus, struct skl, sbus)

/* to pass dai dma data */

struct skl_dma_params {
	
u32 format;
	
u8 stream_tag;
};


struct skl_machine_pdata {
	
u32 dmic_num;
	
bool use_tplg_pcm; /* use dais and dai links from topology */
};


struct skl_dsp_ops {
	
int id;
	
unsigned int num_cores;
	
struct skl_dsp_loader_ops (*loader_ops)(void);
	
int (*init)(struct device *dev, void __iomem *mmio_base,
			int irq, const char *fw_name,
			struct skl_dsp_loader_ops loader_ops,
			struct skl_sst **skl_sst);
	
int (*init_fw)(struct device *dev, struct skl_sst *ctx);
	
void (*cleanup)(struct device *dev, struct skl_sst *ctx);
};

int skl_platform_unregister(struct device *dev);
int skl_platform_register(struct device *dev);

struct nhlt_acpi_table *skl_nhlt_init(struct device *dev);
void skl_nhlt_free(struct nhlt_acpi_table *addr);
struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
					u8 link_type, u8 s_fmt, u8 no_ch,
					u32 s_rate, u8 dirn, u8 dev_type);

int skl_get_dmic_geo(struct skl *skl);
int skl_nhlt_update_topology_bin(struct skl *skl);
int skl_init_dsp(struct skl *skl);
int skl_free_dsp(struct skl *skl);
int skl_suspend_late_dsp(struct skl *skl);
int skl_suspend_dsp(struct skl *skl);
int skl_resume_dsp(struct skl *skl);
void skl_cleanup_resources(struct skl *skl);
const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
void skl_update_d0i3c(struct device *dev, bool enable);
int skl_nhlt_create_sysfs(struct skl *skl);
void skl_nhlt_remove_sysfs(struct skl *skl);
void skl_get_clks(struct skl *skl, struct skl_ssp_clk *ssp_clks);
struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id);
int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps,
				u32 caps_size, u32 node_id);

struct skl_module_cfg;

#ifdef CONFIG_DEBUG_FS
struct skl_debug *skl_debugfs_init(struct skl *skl);
void skl_debug_init_module(struct skl_debug *d,
			struct snd_soc_dapm_widget *w,
			struct skl_module_cfg *mconfig);
#else


static inline struct skl_debug *skl_debugfs_init(struct skl *skl)
{
	return NULL;
}
Contributors
Person
Tokens
Prop
Commits
CommitProp
Vinod Koul
17
100.00%
1
100.00%
Total
17
100.00%
1
100.00%



static inline void skl_debug_init_module(struct skl_debug *d,
					 struct snd_soc_dapm_widget *w,
					 struct skl_module_cfg *mconfig)
{}
Contributors
Person
Tokens
Prop
Commits
CommitProp
Vinod Koul
21
100.00%
1
100.00%
Total
21
100.00%
1
100.00%

#endif

#endif /* __SOUND_SOC_SKL_H */
Overall Contributors
Person
Tokens
Prop
Commits
CommitProp
Jeeja KP
291
41.57%
8
23.53%
Vinod Koul
157
22.43%
9
26.47%
Sriram Periyasamy
66
9.43%
2
5.88%
Pradeep Tewani
44
6.29%
1
2.94%
Dharageswari R
24
3.43%
3
8.82%
Pardha Saradhi K
23
3.29%
1
2.94%
Subhransu S. Prusty
18
2.57%
1
2.94%
Yong Zhi
17
2.43%
1
2.94%
Jayachandran B
17
2.43%
2
5.88%
Guneshwor Singh
12
1.71%
1
2.94%
Sanyog Kale
12
1.71%
1
2.94%
Shreyas NC
9
1.29%
1
2.94%
Pankaj Bharadiya
5
0.71%
1
2.94%
Senthilnathan Veppur
3
0.43%
1
2.94%
Kuninori Morimoto
2
0.29%
1
2.94%
Total
700
100.00%
34
100.00%
Directory: sound/soc/intel/skylake

Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.