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Release 4.18 arch/x86/include/asm/spec-ctrl.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_SPECCTRL_H_

#define _ASM_X86_SPECCTRL_H_

#include <linux/thread_info.h>
#include <asm/nospec-branch.h>

/*
 * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
 * the guest has, while on VMEXIT we restore the host view. This
 * would be easier if SPEC_CTRL were architecturally maskable or
 * shadowable for guests but this is not (currently) the case.
 * Takes the guest view of SPEC_CTRL MSR as a parameter and also
 * the guest's version of VIRT_SPEC_CTRL, if emulated.
 */
extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest);

/**
 * x86_spec_ctrl_set_guest - Set speculation control registers for the guest
 * @guest_spec_ctrl:            The guest content of MSR_SPEC_CTRL
 * @guest_virt_spec_ctrl:       The guest controlled bits of MSR_VIRT_SPEC_CTRL
 *                              (may get translated to MSR_AMD64_LS_CFG bits)
 *
 * Avoids writing to the MSR if the content/bits are the same
 */

static inline void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) { x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, true); }

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Borislav Petkov22100.00%1100.00%
Total22100.00%1100.00%

/** * x86_spec_ctrl_restore_host - Restore host speculation control registers * @guest_spec_ctrl: The guest content of MSR_SPEC_CTRL * @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL * (may get translated to MSR_AMD64_LS_CFG bits) * * Avoids writing to the MSR if the content/bits are the same */
static inline void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) { x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, false); }

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Borislav Petkov1359.09%133.33%
Thomas Gleixner940.91%266.67%
Total22100.00%3100.00%

/* AMD specific Speculative Store Bypass MSR data */ extern u64 x86_amd_ls_cfg_base; extern u64 x86_amd_ls_cfg_ssbd_mask;
static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn) { BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); }

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Thomas Gleixner2480.00%150.00%
Konrad Rzeszutek Wilk620.00%150.00%
Total30100.00%2100.00%


static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl) { BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); }

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Thomas Gleixner31100.00%1100.00%
Total31100.00%1100.00%


static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn) { return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL; }

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Thomas Gleixner1885.71%150.00%
Konrad Rzeszutek Wilk314.29%150.00%
Total21100.00%2100.00%

#ifdef CONFIG_SMP extern void speculative_store_bypass_ht_init(void); #else
static inline void speculative_store_bypass_ht_init(void) { }

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Thomas Gleixner8100.00%1100.00%
Total8100.00%1100.00%

#endif extern void speculative_store_bypass_update(unsigned long tif);
static inline void speculative_store_bypass_update_current(void) { speculative_store_bypass_update(current_thread_info()->flags); }

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Thomas Gleixner17100.00%1100.00%
Total17100.00%1100.00%

#endif

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PersonTokensPropCommitsCommitProp
Thomas Gleixner16476.28%675.00%
Borislav Petkov4119.07%112.50%
Konrad Rzeszutek Wilk104.65%112.50%
Total215100.00%8100.00%
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