cregit-Linux how code gets into the kernel

Release 4.18 arch/x86/kernel/cpu/centaur.c

Directory: arch/x86/kernel/cpu
// SPDX-License-Identifier: GPL-2.0

#include <linux/sched.h>
#include <linux/sched/clock.h>

#include <asm/cpufeature.h>
#include <asm/e820/api.h>
#include <asm/mtrr.h>
#include <asm/msr.h>

#include "cpu.h"


#define ACE_PRESENT	(1 << 6)

#define ACE_ENABLED	(1 << 7)

#define ACE_FCR		(1 << 28)	
/* MSR_VIA_FCR */


#define RNG_PRESENT	(1 << 2)

#define RNG_ENABLED	(1 << 3)

#define RNG_ENABLE	(1 << 6)	
/* MSR_VIA_RNG */


#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000

#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000

#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000

#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001

#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002

#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020




static void init_c3(struct cpuinfo_x86 *c)
{
	u32  lo, hi;

	/* Test for Centaur Extended Feature Flags presence */
	if (cpuid_eax(0xC0000000) >= 0xC0000001) {
		u32 tmp = cpuid_edx(0xC0000001);

		/* enable ACE unit, if present and disabled */
		if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
			rdmsr(MSR_VIA_FCR, lo, hi);
			lo |= ACE_FCR;		/* enable ACE unit */
			wrmsr(MSR_VIA_FCR, lo, hi);
			pr_info("CPU: Enabled ACE h/w crypto\n");
		}

		/* enable RNG unit, if present and disabled */
		if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
			rdmsr(MSR_VIA_RNG, lo, hi);
			lo |= RNG_ENABLE;	/* enable RNG unit */
			wrmsr(MSR_VIA_RNG, lo, hi);
			pr_info("CPU: Enabled h/w RNG\n");
		}

		/* store Centaur Extended Feature Flags as
                 * word 5 of the CPU capability bit array
                 */
		c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
	}
#ifdef CONFIG_X86_32
	/* Cyrix III family needs CX8 & PGE explicitly enabled. */
	if (c->x86_model >= 6 && c->x86_model <= 13) {
		rdmsr(MSR_VIA_FCR, lo, hi);
		lo |= (1<<1 | 1<<7);
		wrmsr(MSR_VIA_FCR, lo, hi);
		set_cpu_cap(c, X86_FEATURE_CX8);
	}

	/* Before Nehemiah, the C3's had 3dNOW! */
	if (c->x86_model >= 6 && c->x86_model < 9)
		set_cpu_cap(c, X86_FEATURE_3DNOW);
#endif
	if (c->x86 == 0x6 && c->x86_model >= 0xf) {
		c->x86_cache_alignment = c->x86_clflush_size * 2;
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	}

	cpu_detect_cache_sizes(c);
}


Contributors
PersonTokensPropCommitsCommitProp
Jeff Garzik18471.32%220.00%


Sebastian Andrzej Siewior3814.73%110.00%


Dave Jones249.30%110.00%


Ingo Molnar62.33%110.00%


Chen Yucong20.78%110.00%


Borislav Petkov20.78%220.00%


Simon Arlott10.39%110.00%


Timo Teräs10.39%110.00%


Total258100.00%10100.00%




enum {
		
ECX8		= 1<<1,
		
EIERRINT	= 1<<2,
		
DPM		= 1<<3,
		
DMCE		= 1<<4,
		
DSTPCLK		= 1<<5,
		
ELINEAR		= 1<<6,
		
DSMC		= 1<<7,
		
DTLOCK		= 1<<8,
		
EDCTLB		= 1<<8,
		
EMMX		= 1<<9,
		
DPDC		= 1<<11,
		
EBRPRED		= 1<<12,
		
DIC		= 1<<13,
		
DDC		= 1<<14,
		
DNA		= 1<<15,
		
ERETSTK		= 1<<16,
		
E2MMX		= 1<<19,
		
EAMD3D		= 1<<20,
};




static void early_init_centaur(struct cpuinfo_x86 *c)
{
	switch (c->x86) {
#ifdef CONFIG_X86_32
	case 5:
		/* Emulate MTRRs using Centaur's MCR. */
		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
		break;
#endif
	case 6:
		if (c->x86_model >= 0xf)
			set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		break;
	}
#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
	if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
	}
}


Contributors
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Sebastian Andrzej Siewior3637.89%133.33%


Yinghai Lu3132.63%133.33%


David Wang2829.47%133.33%


Total95100.00%3100.00%






static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
{
	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	msr_ctl = vmx_msr_high | vmx_msr_low;

	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
		set_cpu_cap(c, X86_FEATURE_VNMI);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
		      vmx_msr_low, vmx_msr_high);
		msr_ctl2 = vmx_msr_high | vmx_msr_low;
		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
			set_cpu_cap(c, X86_FEATURE_EPT);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
			set_cpu_cap(c, X86_FEATURE_VPID);
	}
}


Contributors
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David Wang131100.00%1100.00%


Total131100.00%1100.00%






static void init_centaur(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	char *name;
	u32  fcr_set = 0;
	u32  fcr_clr = 0;
	u32  lo, hi, newlo;
	u32  aa, bb, cc, dd;

	/*
         * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
         * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
         */
	clear_cpu_cap(c, 0*32+31);
#endif
	early_init_centaur(c);
	init_intel_cacheinfo(c);
	detect_num_cpu_cores(c);
#ifdef CONFIG_X86_32
	detect_ht(c);
#endif

	if (c->cpuid_level > 9) {
		unsigned int eax = cpuid_eax(10);

		/*
                 * Check for version and the number of counters
                 * Version(eax[7:0]) can't be 0;
                 * Counters(eax[15:8]) should be greater than 1;
                 */
		if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	switch (c->x86) {
#ifdef CONFIG_X86_32
	case 5:
		switch (c->x86_model) {
		case 4:
			name = "C6";
			fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
			fcr_clr = DPDC;
			pr_notice("Disabling bugged TSC.\n");
			clear_cpu_cap(c, X86_FEATURE_TSC);
			break;
		case 8:
			switch (c->x86_stepping) {
			default:
			name = "2";
				break;
			case 7 ... 9:
				name = "2A";
				break;
			case 10 ... 15:
				name = "2B";
				break;
			}
			fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
				  E2MMX|EAMD3D;
			fcr_clr = DPDC;
			break;
		case 9:
			name = "3";
			fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
				  E2MMX|EAMD3D;
			fcr_clr = DPDC;
			break;
		default:
			name = "??";
		}

		rdmsr(MSR_IDT_FCR1, lo, hi);
		newlo = (lo|fcr_set) & (~fcr_clr);

		if (newlo != lo) {
			pr_info("Centaur FCR was 0x%X now 0x%X\n",
				lo, newlo);
			wrmsr(MSR_IDT_FCR1, newlo, hi);
		} else {
			pr_info("Centaur FCR is 0x%X\n", lo);
		}
		/* Emulate MTRRs using Centaur's MCR. */
		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
		/* Report CX8 */
		set_cpu_cap(c, X86_FEATURE_CX8);
		/* Set 3DNow! on Winchip 2 and above. */
		if (c->x86_model >= 8)
			set_cpu_cap(c, X86_FEATURE_3DNOW);
		/* See if we can find out some more. */
		if (cpuid_eax(0x80000000) >= 0x80000005) {
			/* Yes, we can. */
			cpuid(0x80000005, &aa, &bb, &cc, &dd);
			/* Add L1 data and code cache sizes. */
			c->x86_cache_size = (cc>>24)+(dd>>24);
		}
		sprintf(c->x86_model_id, "WinChip %s", name);
		break;
#endif
	case 6:
		init_c3(c);
		break;
	}
#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
#endif

	if (cpu_has(c, X86_FEATURE_VMX))
		centaur_detect_vmx_virtcap(c);
}


Contributors
PersonTokensPropCommitsCommitProp
Dave Jones33070.06%111.11%


David Wang8317.62%222.22%


Sebastian Andrzej Siewior275.73%111.11%


Ingo Molnar265.52%222.22%


Chen Yucong30.64%111.11%


Jeff Garzik10.21%111.11%


jia zhang10.21%111.11%


Total471100.00%9100.00%



#ifdef CONFIG_X86_32


static unsigned int

centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/* VIA C3 CPUs (670-68F) need further shifting. */
	if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
		size >>= 8;

	/*
         * There's also an erratum in Nehemiah stepping 1, which
         * returns '65KB' instead of '64KB'
         *  - Note, it seems this may only be in engineering samples.
         */
	if ((c->x86 == 6) && (c->x86_model == 9) &&
				(c->x86_stepping == 1) && (size == 65))
		size -= 1;
	return size;
}

Contributors
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Dave Jones8797.75%360.00%


jia zhang11.12%120.00%


Ingo Molnar11.12%120.00%


Total89100.00%5100.00%



#endif


static const struct cpu_dev centaur_cpu_dev = {
	.c_vendor	= "Centaur",
	.c_ident	= { "CentaurHauls" },
	.c_early_init	= early_init_centaur,
	.c_init		= init_centaur,
#ifdef CONFIG_X86_32
	.legacy_cache_size = centaur_size_cache,
#endif
	.c_x86_vendor	= X86_VENDOR_CENTAUR,
};

cpu_dev_register(centaur_cpu_dev);

Overall Contributors
PersonTokensPropCommitsCommitProp
Dave Jones58245.40%412.90%


David Wang26620.75%39.68%


Jeff Garzik21116.46%26.45%


Sebastian Andrzej Siewior1038.03%13.23%


Yinghai Lu423.28%26.45%


Ingo Molnar382.96%412.90%


Jan Beulich120.94%26.45%


Rusty Russell80.62%13.23%


Chen Yucong50.39%13.23%


Borislav Petkov30.23%39.68%


jia zhang20.16%13.23%


Jesper Juhl20.16%13.23%


Thomas Petazzoni20.16%13.23%


James McMechan20.16%13.23%


Greg Kroah-Hartman10.08%13.23%


Simon Arlott10.08%13.23%


Timo Teräs10.08%13.23%


Peter Zijlstra10.08%13.23%


Thomas Gleixner0.00%00.00%


Total1282100.00%31100.00%


Directory: arch/x86/kernel/cpu



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