cregit-Linux how code gets into the kernel

Release 4.7 drivers/clk/clk-mux.c

Directory: drivers/clk
/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Simple multiplexer clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>

/*
 * DOC: basic adjustable multiplexer clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is only affected by parent switching.  No clk_set_rate support
 * parent - parent is adjustable through clk_set_parent
 */


static u8 clk_mux_get_parent(struct clk_hw *hw) { struct clk_mux *mux = to_clk_mux(hw); int num_parents = clk_hw_get_num_parents(hw); u32 val; /* * FIXME need a mux-specific flag to determine if val is bitwise or numeric * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 * to 0x7 (index starts at one) * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so * val = 0x4 really means "bit 2, index starts at bit 0" */ val = clk_readl(mux->reg) >> mux->shift; val &= mux->mask; if (mux->table) { int i; for (i = 0; i < num_parents; i++) if (mux->table[i] == val) return i; return -EINVAL; } if (val && (mux->flags & CLK_MUX_INDEX_BIT)) val = ffs(val) - 1; if (val && (mux->flags & CLK_MUX_INDEX_ONE)) val--; if (val >= num_parents) return -EINVAL; return val; }

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michael turquettemichael turquette9062.94%125.00%
peter de schrijverpeter de schrijver5135.66%125.00%
gerhard sittiggerhard sittig10.70%125.00%
stephen boydstephen boyd10.70%125.00%
Total143100.00%4100.00%


static int clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct clk_mux *mux = to_clk_mux(hw); u32 val; unsigned long flags = 0; if (mux->table) { index = mux->table[index]; } else { if (mux->flags & CLK_MUX_INDEX_BIT) index = 1 << index; if (mux->flags & CLK_MUX_INDEX_ONE) index++; } if (mux->lock) spin_lock_irqsave(mux->lock, flags); else __acquire(mux->lock); if (mux->flags & CLK_MUX_HIWORD_MASK) { val = mux->mask << (mux->shift + 16); } else { val = clk_readl(mux->reg); val &= ~(mux->mask << mux->shift); } val |= index << mux->shift; clk_writel(val, mux->reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); else __release(mux->lock); return 0; }

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michael turquettemichael turquette12765.80%116.67%
haojian zhuanghaojian zhuang2713.99%116.67%
peter de schrijverpeter de schrijver199.84%116.67%
stephen boydstephen boyd168.29%116.67%
masahiro yamadamasahiro yamada21.04%116.67%
gerhard sittiggerhard sittig21.04%116.67%
Total193100.00%6100.00%

const struct clk_ops clk_mux_ops = { .get_parent = clk_mux_get_parent, .set_parent = clk_mux_set_parent, .determine_rate = __clk_mux_determine_rate, }; EXPORT_SYMBOL_GPL(clk_mux_ops); const struct clk_ops clk_mux_ro_ops = { .get_parent = clk_mux_get_parent, }; EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_mux *mux; struct clk_hw *hw; struct clk_init_data init; u8 width = 0; int ret; if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { width = fls(mask) - ffs(mask) + 1; if (width + shift > 16) { pr_err("mux value exceeds LOWORD field\n"); return ERR_PTR(-EINVAL); } } /* allocate the mux */ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); if (!mux) { pr_err("%s: could not allocate mux clk\n", __func__); return ERR_PTR(-ENOMEM); } init.name = name; if (clk_mux_flags & CLK_MUX_READ_ONLY) init.ops = &clk_mux_ro_ops; else init.ops = &clk_mux_ops; init.flags = flags | CLK_IS_BASIC; init.parent_names = parent_names; init.num_parents = num_parents; /* struct clk_mux assignments */ mux->reg = reg; mux->shift = shift; mux->mask = mask; mux->flags = clk_mux_flags; mux->lock = lock; mux->table = table; mux->hw.init = &init; hw = &mux->hw; ret = clk_hw_register(dev, hw); if (ret) { kfree(mux); hw = ERR_PTR(ret); } return hw; }

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michael turquettemichael turquette12845.07%325.00%
haojian zhuanghaojian zhuang4917.25%18.33%
stephen boydstephen boyd3913.73%18.33%
saravana kannansaravana kannan3512.32%18.33%
tomasz figatomasz figa144.93%18.33%
peter de schrijverpeter de schrijver144.93%18.33%
rajendra nayakrajendra nayak20.70%18.33%
mark brownmark brown10.35%18.33%
sascha hauersascha hauer10.35%18.33%
shawn guoshawn guo10.35%18.33%
Total284100.00%12100.00%

EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock) { struct clk_hw *hw; hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, table, lock); if (IS_ERR(hw)) return ERR_CAST(hw); return hw->clk; }

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stephen boydstephen boyd8986.41%133.33%
michael turquettemichael turquette1413.59%266.67%
Total103100.00%3100.00%

EXPORT_SYMBOL_GPL(clk_register_mux_table);
struct clk *clk_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock) { u32 mask = BIT(width) - 1; return clk_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, NULL, lock); }

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peter de schrijverpeter de schrijver8498.82%150.00%
sascha hauersascha hauer11.18%150.00%
Total85100.00%2100.00%

EXPORT_SYMBOL_GPL(clk_register_mux);
struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock) { u32 mask = BIT(width) - 1; return clk_hw_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, NULL, lock); }

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stephen boydstephen boyd85100.00%1100.00%
Total85100.00%1100.00%

EXPORT_SYMBOL_GPL(clk_hw_register_mux);
void clk_unregister_mux(struct clk *clk) { struct clk_mux *mux; struct clk_hw *hw; hw = __clk_get_hw(clk); if (!hw) return; mux = to_clk_mux(hw); clk_unregister(clk); kfree(mux); }

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krzysztof kozlowskikrzysztof kozlowski50100.00%1100.00%
Total50100.00%1100.00%

EXPORT_SYMBOL_GPL(clk_unregister_mux);
void clk_hw_unregister_mux(struct clk_hw *hw) { struct clk_mux *mux; mux = to_clk_mux(hw); clk_hw_unregister(hw); kfree(mux); }

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stephen boydstephen boyd32100.00%1100.00%
Total32100.00%1100.00%

EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);

Overall Contributors

PersonTokensPropCommitsCommitProp
michael turquettemichael turquette40738.18%420.00%
stephen boydstephen boyd27725.98%315.00%
peter de schrijverpeter de schrijver16815.76%15.00%
haojian zhuanghaojian zhuang767.13%15.00%
krzysztof kozlowskikrzysztof kozlowski555.16%15.00%
saravana kannansaravana kannan353.28%15.00%
tomasz figatomasz figa312.91%15.00%
james hoganjames hogan50.47%15.00%
gerhard sittiggerhard sittig30.28%15.00%
rajendra nayakrajendra nayak20.19%15.00%
sascha hauersascha hauer20.19%15.00%
shawn guoshawn guo20.19%210.00%
masahiro yamadamasahiro yamada20.19%15.00%
mark brownmark brown10.09%15.00%
Total1066100.00%20100.00%
Directory: drivers/clk
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