Release 4.7 drivers/clk/imx/clk-gate2.c
/*
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Gated clock implementation
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include "clk.h"
/**
* DOC: basic gatable clock which can gate and ungate it's ouput
*
* Traits of this clock:
* prepare - clk_(un)prepare only ensures parent is (un)prepared
* enable - clk_enable and clk_disable are functional & control gating
* rate - inherits rate from parent. No clk_set_rate support
* parent - fixed parent. No clk_set_parent support
*/
struct clk_gate2 {
struct clk_hw hw;
void __iomem *reg;
u8 bit_idx;
u8 cgr_val;
u8 flags;
spinlock_t *lock;
unsigned int *share_count;
};
#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
static int clk_gate2_enable(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
u32 reg;
unsigned long flags = 0;
spin_lock_irqsave(gate->lock, flags);
if (gate->share_count && (*gate->share_count)++ > 0)
goto out;
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
reg |= gate->cgr_val << gate->bit_idx;
writel(reg, gate->reg);
out:
spin_unlock_irqrestore(gate->lock, flags);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| sascha hauer | sascha hauer | 74 | 66.67% | 1 | 25.00% |
| shawn guo | shawn guo | 23 | 20.72% | 2 | 50.00% |
| stefan agner | stefan agner | 14 | 12.61% | 1 | 25.00% |
| Total | 111 | 100.00% | 4 | 100.00% |
static void clk_gate2_disable(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
u32 reg;
unsigned long flags = 0;
spin_lock_irqsave(gate->lock, flags);
if (gate->share_count) {
if (WARN_ON(*gate->share_count == 0))
goto out;
else if (--(*gate->share_count) > 0)
goto out;
}
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
writel(reg, gate->reg);
out:
spin_unlock_irqrestore(gate->lock, flags);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| sascha hauer | sascha hauer | 75 | 63.56% | 1 | 25.00% |
| shawn guo | shawn guo | 43 | 36.44% | 3 | 75.00% |
| Total | 118 | 100.00% | 4 | 100.00% |
static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
{
u32 val = readl(reg);
if (((val >> bit_idx) & 1) == 1)
return 1;
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| sascha hauer | sascha hauer | 30 | 71.43% | 1 | 33.33% |
| shawn guo | shawn guo | 10 | 23.81% | 1 | 33.33% |
| anson huang | anson huang | 2 | 4.76% | 1 | 33.33% |
| Total | 42 | 100.00% | 3 | 100.00% |
static int clk_gate2_is_enabled(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| shawn guo | shawn guo | 20 | 60.61% | 1 | 50.00% |
| anson huang | anson huang | 13 | 39.39% | 1 | 50.00% |
| Total | 33 | 100.00% | 2 | 100.00% |
static void clk_gate2_disable_unused(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
unsigned long flags = 0;
u32 reg;
spin_lock_irqsave(gate->lock, flags);
if (!gate->share_count || *gate->share_count == 0) {
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
writel(reg, gate->reg);
}
spin_unlock_irqrestore(gate->lock, flags);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| anson huang | anson huang | 76 | 81.72% | 1 | 33.33% |
| shawn guo | shawn guo | 17 | 18.28% | 2 | 66.67% |
| Total | 93 | 100.00% | 3 | 100.00% |
static struct clk_ops clk_gate2_ops = {
.enable = clk_gate2_enable,
.disable = clk_gate2_disable,
.disable_unused = clk_gate2_disable_unused,
.is_enabled = clk_gate2_is_enabled,
};
struct clk *clk_register_gate2(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx, u8 cgr_val,
u8 clk_gate2_flags, spinlock_t *lock,
unsigned int *share_count)
{
struct clk_gate2 *gate;
struct clk *clk;
struct clk_init_data init;
gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
/* struct clk_gate2 assignments */
gate->reg = reg;
gate->bit_idx = bit_idx;
gate->cgr_val = cgr_val;
gate->flags = clk_gate2_flags;
gate->lock = lock;
gate->share_count = share_count;
init.name = name;
init.ops = &clk_gate2_ops;
init.flags = flags;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
gate->hw.init = &init;
clk = clk_register(dev, &gate->hw);
if (IS_ERR(clk))
kfree(gate);
return clk;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| sascha hauer | sascha hauer | 177 | 88.06% | 1 | 20.00% |
| shawn guo | shawn guo | 14 | 6.97% | 2 | 40.00% |
| stefan agner | stefan agner | 9 | 4.48% | 1 | 20.00% |
| wei yongjun | wei yongjun | 1 | 0.50% | 1 | 20.00% |
| Total | 201 | 100.00% | 5 | 100.00% |
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| sascha hauer | sascha hauer | 403 | 58.66% | 1 | 10.00% |
| shawn guo | shawn guo | 158 | 23.00% | 4 | 40.00% |
| anson huang | anson huang | 96 | 13.97% | 2 | 20.00% |
| stefan agner | stefan agner | 26 | 3.78% | 1 | 10.00% |
| fabio estevam | fabio estevam | 3 | 0.44% | 1 | 10.00% |
| wei yongjun | wei yongjun | 1 | 0.15% | 1 | 10.00% |
| Total | 687 | 100.00% | 10 | 100.00% |
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