Release 4.7 drivers/gpu/drm/i915/intel_sideband.c

Directory: drivers/gpu/drm/i915
/*
 * Copyright Â© 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

/*
 * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
 * VLV_VLV2_PUNIT_HAS_0.8.docx
 */

/* Standard MMIO read, non-posted */

#define SB_MRD_NP	0x00
/* Standard MMIO write, non-posted */

#define SB_MWR_NP	0x01
/* Private register read, double-word addressing, non-posted */

#define SB_CRRDDA_NP	0x06
/* Private register write, double-word addressing, non-posted */

#define SB_CRWRDA_NP	0x07



static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
			   u32 port, u32 opcode, u32 addr, u32 *val)
{
	u32 cmd, be = 0xf, bar = 0;
	bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);

	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
		(bar << IOSF_BAR_SHIFT);

	WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));

	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
		DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
				 is_read ? "read" : "write");
		return -EAGAIN;
	}

	I915_WRITE(VLV_IOSF_ADDR, addr);
	if (!is_read)
		I915_WRITE(VLV_IOSF_DATA, *val);
	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);

	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
		DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
				 is_read ? "read" : "write");
		return -ETIMEDOUT;
	}

	if (is_read)
		*val = I915_READ(VLV_IOSF_DATA);
	I915_WRITE(VLV_IOSF_DATA, 0);

	return 0;
}

Contributors
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jani nikula jani nikula 211 98.60% 2 50.00%
imre deak imre deak 2 0.93% 1 25.00%
ville syrjala ville syrjala 1 0.47% 1 25.00%
Total 214 100.00% 4 100.00%



u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
{
	u32 val = 0;

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	mutex_lock(&dev_priv->sb_lock);
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
			SB_CRRDDA_NP, addr, &val);
	mutex_unlock(&dev_priv->sb_lock);

	return val;
}

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jani nikula jani nikula 67 93.06% 4 50.00%
ville syrjala ville syrjala 2 2.78% 1 12.50%
deepak s deepak s 1 1.39% 1 12.50%
shobhit kumar shobhit kumar 1 1.39% 1 12.50%
imre deak imre deak 1 1.39% 1 12.50%
Total 72 100.00% 8 100.00%



void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
{
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	mutex_lock(&dev_priv->sb_lock);
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
			SB_CRWRDA_NP, addr, &val);
	mutex_unlock(&dev_priv->sb_lock);
}

Contributors
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jani nikula jani nikula 62 92.54% 4 50.00%
ville syrjala ville syrjala 2 2.99% 1 12.50%
deepak s deepak s 1 1.49% 1 12.50%
imre deak imre deak 1 1.49% 1 12.50%
shobhit kumar shobhit kumar 1 1.49% 1 12.50%
Total 67 100.00% 8 100.00%



u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
{
	u32 val = 0;

	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
			SB_CRRDDA_NP, reg, &val);

	return val;
}

Contributors
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jesse barnes jesse barnes 40 95.24% 1 33.33%
imre deak imre deak 1 2.38% 1 33.33%
shobhit kumar shobhit kumar 1 2.38% 1 33.33%
Total 42 100.00% 3 100.00%



void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
			SB_CRWRDA_NP, reg, &val);
}

Contributors
Person Tokens Prop Commits CommitProp
jesse barnes jesse barnes 35 94.59% 1 33.33%
shobhit kumar shobhit kumar 1 2.70% 1 33.33%
imre deak imre deak 1 2.70% 1 33.33%
Total 37 100.00% 3 100.00%



u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{
	u32 val = 0;

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	mutex_lock(&dev_priv->sb_lock);
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
			SB_CRRDDA_NP, addr, &val);
	mutex_unlock(&dev_priv->sb_lock);

	return val;
}

Contributors
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jani nikula jani nikula 68 94.44% 4 57.14%
ville syrjala ville syrjala 2 2.78% 1 14.29%
imre deak imre deak 1 1.39% 1 14.29%
shobhit kumar shobhit kumar 1 1.39% 1 14.29%
Total 72 100.00% 7 100.00%



u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
{
	u32 val = 0;
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
			SB_CRRDDA_NP, reg, &val);
	return val;
}

Contributors
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jani nikula jani nikula 38 84.44% 1 25.00%
deepak m deepak m 5 11.11% 1 25.00%
imre deak imre deak 1 2.22% 1 25.00%
shobhit kumar shobhit kumar 1 2.22% 1 25.00%
Total 45 100.00% 4 100.00%



void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
		       u8 port, u32 reg, u32 val)
{
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
			SB_CRWRDA_NP, reg, &val);
}

Contributors
Person Tokens Prop Commits CommitProp
jani nikula jani nikula 33 82.50% 1 25.00%
deepak m deepak m 5 12.50% 1 25.00%
imre deak imre deak 1 2.50% 1 25.00%
shobhit kumar shobhit kumar 1 2.50% 1 25.00%
Total 40 100.00% 4 100.00%



u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
{
	u32 val = 0;
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
			SB_CRRDDA_NP, reg, &val);
	return val;
}

Contributors
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jani nikula jani nikula 40 95.24% 1 33.33%
shobhit kumar shobhit kumar 1 2.38% 1 33.33%
imre deak imre deak 1 2.38% 1 33.33%
Total 42 100.00% 3 100.00%



void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
			SB_CRWRDA_NP, reg, &val);
}

Contributors
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jani nikula jani nikula 35 94.59% 1 33.33%
imre deak imre deak 1 2.70% 1 33.33%
shobhit kumar shobhit kumar 1 2.70% 1 33.33%
Total 37 100.00% 3 100.00%



u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
{
	u32 val = 0;
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
			SB_CRRDDA_NP, reg, &val);
	return val;
}

Contributors
Person Tokens Prop Commits CommitProp
jani nikula jani nikula 40 95.24% 1 33.33%
imre deak imre deak 1 2.38% 1 33.33%
shobhit kumar shobhit kumar 1 2.38% 1 33.33%
Total 42 100.00% 3 100.00%



void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
			SB_CRWRDA_NP, reg, &val);
}

Contributors
Person Tokens Prop Commits CommitProp
jani nikula jani nikula 35 94.59% 1 33.33%
shobhit kumar shobhit kumar 1 2.70% 1 33.33%
imre deak imre deak 1 2.70% 1 33.33%
Total 37 100.00% 3 100.00%



u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
{
	u32 val = 0;

	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
			SB_MRD_NP, reg, &val);

	/*
         * FIXME: There might be some registers where all 1's is a valid value,
         * so ideally we should check the register offset instead...
         */
	WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
	     pipe_name(pipe), reg, val);

	return val;
}

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jani nikula jani nikula 35 53.03% 3 42.86%
ville syrjala ville syrjala 19 28.79% 1 14.29%
chon ming lee chon ming lee 11 16.67% 2 28.57%
imre deak imre deak 1 1.52% 1 14.29%
Total 66 100.00% 7 100.00%



void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
{
	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
			SB_MWR_NP, reg, &val);
}

Contributors
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jani nikula jani nikula 30 71.43% 3 50.00%
chon ming lee chon ming lee 11 26.19% 2 33.33%
imre deak imre deak 1 2.38% 1 16.67%
Total 42 100.00% 6 100.00%

/* SBI access */


u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination)
{
	u32 value = 0;
	WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));

	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
		return 0;
	}

	I915_WRITE(SBI_ADDR, (reg << 16));

	if (destination == SBI_ICLK)
		value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
	else
		value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
	I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);

	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
		return 0;
	}

	return I915_READ(SBI_DATA);
}

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jani nikula jani nikula 138 99.28% 1 50.00%
ville syrjala ville syrjala 1 0.72% 1 50.00%
Total 139 100.00% 2 100.00%



void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination)
{
	u32 tmp;

	WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));

	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
		return;
	}

	I915_WRITE(SBI_ADDR, (reg << 16));
	I915_WRITE(SBI_DATA, value);

	if (destination == SBI_ICLK)
		tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
	else
		tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
	I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);

	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
		return;
	}
}

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ville syrjala ville syrjala 1 0.73% 1 50.00%
Total 137 100.00% 2 100.00%



u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
{
	u32 val = 0;
	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
			reg, &val);
	return val;
}

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shobhit kumar shobhit kumar 36 97.30% 1 50.00%
imre deak imre deak 1 2.70% 1 50.00%
Total 37 100.00% 2 100.00%



void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
			reg, &val);
}
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shobhit kumar shobhit kumar 31 96.88% 1 50.00%
imre deak imre deak 1 3.12% 1 50.00%
Total 32 100.00% 2 100.00%

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jani nikula jani nikula 976 79.41% 5 29.41%
shobhit kumar shobhit kumar 78 6.35% 2 11.76%
jesse barnes jesse barnes 76 6.18% 2 11.76%
imre deak imre deak 37 3.01% 2 11.76%
ville syrjala ville syrjala 28 2.28% 2 11.76%
chon ming lee chon ming lee 22 1.79% 2 11.76%
deepak m deepak m 10 0.81% 1 5.88%
deepak s deepak s 2 0.16% 1 5.88%
Total 1229 100.00% 17 100.00%
  Directory: drivers/gpu/drm/i915

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	Person	Tokens	Prop	Commits	CommitProp
jani nikula	jani nikula	211	98.60%	2	50.00%
imre deak	imre deak	2	0.93%	1	25.00%
ville syrjala	ville syrjala	1	0.47%	1	25.00%
	Total	214	100.00%	4	100.00%
cregit-Linux how code gets into the kernel

Release 4.7 drivers/gpu/drm/i915/intel_sideband.c

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