Release 4.7 drivers/gpu/drm/r128/r128_irq.c
  
  
/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- */
/*
 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
 *
 * The Weather Channel (TM) funded Tungsten Graphics to develop the
 * initial release of the Radeon 8500 driver under the XFree86 license.
 * This notice must be preserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Whitwell <keith@tungstengraphics.com>
 *    Eric Anholt <anholt@FreeBSD.org>
 */
#include <drm/drmP.h>
#include <drm/r128_drm.h>
#include "r128_drv.h"
u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
{
	const drm_r128_private_t *dev_priv = dev->dev_private;
	if (pipe != 0)
		return 0;
	return atomic_read(&dev_priv->vbl_received);
}
Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| jesse barnes | jesse barnes | 38 | 92.68% | 1 | 50.00% | 
| thierry reding | thierry reding | 3 | 7.32% | 1 | 50.00% | 
 | Total | 41 | 100.00% | 2 | 100.00% | 
irqreturn_t r128_driver_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
	int status;
	status = R128_READ(R128_GEN_INT_STATUS);
	/* VBLANK interrupt */
	if (status & R128_CRTC_VBLANK_INT) {
		R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
		atomic_inc(&dev_priv->vbl_received);
		drm_handle_vblank(dev, 0);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}
Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| linus torvalds | linus torvalds | 58 | 69.88% | 2 | 25.00% | 
| dave airlie | dave airlie | 8 | 9.64% | 3 | 37.50% | 
| andrew morton | andrew morton | 7 | 8.43% | 1 | 12.50% | 
| daniel vetter | daniel vetter | 6 | 7.23% | 1 | 12.50% | 
| jesse barnes | jesse barnes | 4 | 4.82% | 1 | 12.50% | 
 | Total | 83 | 100.00% | 8 | 100.00% | 
int r128_enable_vblank(struct drm_device *dev, unsigned int pipe)
{
	drm_r128_private_t *dev_priv = dev->dev_private;
	if (pipe != 0) {
		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
		return -EINVAL;
	}
	R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
	return 0;
}
Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| jesse barnes | jesse barnes | 26 | 49.06% | 1 | 16.67% | 
| linus torvalds | linus torvalds | 16 | 30.19% | 2 | 33.33% | 
| dave airlie | dave airlie | 6 | 11.32% | 2 | 33.33% | 
| thierry reding | thierry reding | 5 | 9.43% | 1 | 16.67% | 
 | Total | 53 | 100.00% | 6 | 100.00% | 
void r128_disable_vblank(struct drm_device *dev, unsigned int pipe)
{
	if (pipe != 0)
		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
	/*
         * FIXME: implement proper interrupt disable by using the vblank
         * counter register (if available)
         *
         * R128_WRITE(R128_GEN_INT_CNTL,
         *            R128_READ(R128_GEN_INT_CNTL) & ~R128_CRTC_VBLANK_INT_EN);
         */
}
Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| jesse barnes | jesse barnes | 25 | 83.33% | 1 | 50.00% | 
| thierry reding | thierry reding | 5 | 16.67% | 1 | 50.00% | 
 | Total | 30 | 100.00% | 2 | 100.00% | 
void r128_driver_irq_preinstall(struct drm_device *dev)
{
	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
	/* Disable *all* interrupts */
	R128_WRITE(R128_GEN_INT_CNTL, 0);
	/* Clear vblank bit if it's already high */
	R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
}
Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| linus torvalds | linus torvalds | 36 | 94.74% | 1 | 50.00% | 
| dave airlie | dave airlie | 2 | 5.26% | 1 | 50.00% | 
 | Total | 38 | 100.00% | 2 | 100.00% | 
int r128_driver_irq_postinstall(struct drm_device *dev)
{
	return 0;
}
Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| linus torvalds | linus torvalds | 7 | 53.85% | 1 | 25.00% | 
| jesse barnes | jesse barnes | 3 | 23.08% | 1 | 25.00% | 
| dave airlie | dave airlie | 2 | 15.38% | 1 | 25.00% | 
| keith packard | keith packard | 1 | 7.69% | 1 | 25.00% | 
 | Total | 13 | 100.00% | 4 | 100.00% | 
void r128_driver_irq_uninstall(struct drm_device *dev)
{
	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
	if (!dev_priv)
		return;
	/* Disable *all* interrupts */
	R128_WRITE(R128_GEN_INT_CNTL, 0);
}
Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| linus torvalds | linus torvalds | 34 | 94.44% | 2 | 66.67% | 
| dave airlie | dave airlie | 2 | 5.56% | 1 | 33.33% | 
 | Total | 36 | 100.00% | 3 | 100.00% | 
Overall Contributors
 | Person | Tokens | Prop | Commits | CommitProp | 
| linus torvalds | linus torvalds | 158 | 51.80% | 3 | 21.43% | 
| jesse barnes | jesse barnes | 96 | 31.48% | 1 | 7.14% | 
| dave airlie | dave airlie | 22 | 7.21% | 5 | 35.71% | 
| thierry reding | thierry reding | 13 | 4.26% | 1 | 7.14% | 
| andrew morton | andrew morton | 7 | 2.30% | 1 | 7.14% | 
| daniel vetter | daniel vetter | 6 | 1.97% | 1 | 7.14% | 
| david howells | david howells | 2 | 0.66% | 1 | 7.14% | 
| keith packard | keith packard | 1 | 0.33% | 1 | 7.14% | 
 | Total | 305 | 100.00% | 14 | 100.00% | 
  
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