Release 4.7 drivers/irqchip/irq-sirfsoc.c
/*
* interrupt controller support for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
#define SIRFSOC_INT_RISC_MASK0 0x0018
#define SIRFSOC_INT_RISC_MASK1 0x001C
#define SIRFSOC_INT_RISC_LEVEL0 0x0020
#define SIRFSOC_INT_RISC_LEVEL1 0x0024
#define SIRFSOC_INIT_IRQ_ID 0x0038
#define SIRFSOC_INT_BASE_OFFSET 0x0004
#define SIRFSOC_NUM_IRQS 64
#define SIRFSOC_NUM_BANKS (SIRFSOC_NUM_IRQS / 32)
static struct irq_domain *sirfsoc_irqdomain;
static __init void sirfsoc_alloc_gc(void __iomem *base)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
unsigned int set = IRQ_LEVEL;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int i;
irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
handle_level_irq, clr, set,
IRQ_GC_INIT_MASK_CACHE);
for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
}
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| binghua duan | binghua duan | 50 | 39.68% | 1 | 25.00% |
| barry song | barry song | 40 | 31.75% | 2 | 50.00% |
| thomas gleixner | thomas gleixner | 36 | 28.57% | 1 | 25.00% |
| Total | 126 | 100.00% | 4 | 100.00% |
static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
{
void __iomem *base = sirfsoc_irqdomain->host_data;
u32 irqstat;
irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| barry song | barry song | 29 | 65.91% | 1 | 33.33% |
| arnd bergmann | arnd bergmann | 14 | 31.82% | 1 | 33.33% |
| marc zyngier | marc zyngier | 1 | 2.27% | 1 | 33.33% |
| Total | 44 | 100.00% | 3 | 100.00% |
static int __init sirfsoc_irq_init(struct device_node *np,
struct device_node *parent)
{
void __iomem *base = of_iomap(np, 0);
if (!base)
panic("unable to map intc cpu registers\n");
sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
&irq_generic_chip_ops, base);
sirfsoc_alloc_gc(base);
writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
set_handle_irq(sirfsoc_handle_irq);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| arnd bergmann | arnd bergmann | 68 | 66.67% | 1 | 20.00% |
| binghua duan | binghua duan | 24 | 23.53% | 1 | 20.00% |
| barry song | barry song | 7 | 6.86% | 2 | 40.00% |
| grant likely | grant likely | 3 | 2.94% | 1 | 20.00% |
| Total | 102 | 100.00% | 5 | 100.00% |
IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
struct sirfsoc_irq_status {
u32 mask0;
u32 mask1;
u32 level0;
u32 level1;
};
static struct sirfsoc_irq_status sirfsoc_irq_st;
static int sirfsoc_irq_suspend(void)
{
void __iomem *base = sirfsoc_irqdomain->host_data;
sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| barry song | barry song | 51 | 79.69% | 1 | 50.00% |
| arnd bergmann | arnd bergmann | 13 | 20.31% | 1 | 50.00% |
| Total | 64 | 100.00% | 2 | 100.00% |
static void sirfsoc_irq_resume(void)
{
void __iomem *base = sirfsoc_irqdomain->host_data;
writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| barry song | barry song | 48 | 78.69% | 1 | 50.00% |
| arnd bergmann | arnd bergmann | 13 | 21.31% | 1 | 50.00% |
| Total | 61 | 100.00% | 2 | 100.00% |
static struct syscore_ops sirfsoc_irq_syscore_ops = {
.suspend = sirfsoc_irq_suspend,
.resume = sirfsoc_irq_resume,
};
static int __init sirfsoc_irq_pm_init(void)
{
if (!sirfsoc_irqdomain)
return 0;
register_syscore_ops(&sirfsoc_irq_syscore_ops);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| barry song | barry song | 18 | 69.23% | 1 | 50.00% |
| arnd bergmann | arnd bergmann | 8 | 30.77% | 1 | 50.00% |
| Total | 26 | 100.00% | 2 | 100.00% |
device_initcall(sirfsoc_irq_pm_init);
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| barry song | barry song | 250 | 45.87% | 5 | 45.45% |
| arnd bergmann | arnd bergmann | 132 | 24.22% | 1 | 9.09% |
| binghua duan | binghua duan | 110 | 20.18% | 1 | 9.09% |
| thomas gleixner | thomas gleixner | 44 | 8.07% | 1 | 9.09% |
| joel porquet | joel porquet | 5 | 0.92% | 1 | 9.09% |
| grant likely | grant likely | 3 | 0.55% | 1 | 9.09% |
| marc zyngier | marc zyngier | 1 | 0.18% | 1 | 9.09% |
| Total | 545 | 100.00% | 11 | 100.00% |
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