Release 4.7 drivers/media/pci/cx23885/cx23888-ir.c
/*
* Driver for the Conexant CX23885/7/8 PCIe bridge
*
* CX23888 Integrated Consumer Infrared Controller
*
* Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kfifo.h>
#include <linux/slab.h>
#include <media/v4l2-device.h>
#include <media/rc-core.h>
#include "cx23885.h"
#include "cx23888-ir.h"
static unsigned int ir_888_debug;
module_param(ir_888_debug, int, 0644);
MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
#define CX23888_IR_REG_BASE 0x170000
/*
* These CX23888 register offsets have a straightforward one to one mapping
* to the CX23885 register offsets of 0x200 through 0x218
*/
#define CX23888_IR_CNTRL_REG 0x170000
#define CNTRL_WIN_3_3 0x00000000
#define CNTRL_WIN_4_3 0x00000001
#define CNTRL_WIN_3_4 0x00000002
#define CNTRL_WIN_4_4 0x00000003
#define CNTRL_WIN 0x00000003
#define CNTRL_EDG_NONE 0x00000000
#define CNTRL_EDG_FALL 0x00000004
#define CNTRL_EDG_RISE 0x00000008
#define CNTRL_EDG_BOTH 0x0000000C
#define CNTRL_EDG 0x0000000C
#define CNTRL_DMD 0x00000010
#define CNTRL_MOD 0x00000020
#define CNTRL_RFE 0x00000040
#define CNTRL_TFE 0x00000080
#define CNTRL_RXE 0x00000100
#define CNTRL_TXE 0x00000200
#define CNTRL_RIC 0x00000400
#define CNTRL_TIC 0x00000800
#define CNTRL_CPL 0x00001000
#define CNTRL_LBM 0x00002000
#define CNTRL_R 0x00004000
/* CX23888 specific control flag */
#define CNTRL_IVO 0x00008000
#define CX23888_IR_TXCLK_REG 0x170004
#define TXCLK_TCD 0x0000FFFF
#define CX23888_IR_RXCLK_REG 0x170008
#define RXCLK_RCD 0x0000FFFF
#define CX23888_IR_CDUTY_REG 0x17000C
#define CDUTY_CDC 0x0000000F
#define CX23888_IR_STATS_REG 0x170010
#define STATS_RTO 0x00000001
#define STATS_ROR 0x00000002
#define STATS_RBY 0x00000004
#define STATS_TBY 0x00000008
#define STATS_RSR 0x00000010
#define STATS_TSR 0x00000020
#define CX23888_IR_IRQEN_REG 0x170014
#define IRQEN_RTE 0x00000001
#define IRQEN_ROE 0x00000002
#define IRQEN_RSE 0x00000010
#define IRQEN_TSE 0x00000020
#define CX23888_IR_FILTR_REG 0x170018
#define FILTR_LPF 0x0000FFFF
/* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
#define CX23888_IR_FIFO_REG 0x170040
#define FIFO_RXTX 0x0000FFFF
#define FIFO_RXTX_LVL 0x00010000
#define FIFO_RXTX_RTO 0x0001FFFF
#define FIFO_RX_NDV 0x00020000
#define FIFO_RX_DEPTH 8
#define FIFO_TX_DEPTH 8
/* CX23888 unique registers */
#define CX23888_IR_SEEDP_REG 0x17001C
#define CX23888_IR_TIMOL_REG 0x170020
#define CX23888_IR_WAKE0_REG 0x170024
#define CX23888_IR_WAKE1_REG 0x170028
#define CX23888_IR_WAKE2_REG 0x17002C
#define CX23888_IR_MASK0_REG 0x170030
#define CX23888_IR_MASK1_REG 0x170034
#define CX23888_IR_MAKS2_REG 0x170038
#define CX23888_IR_DPIPG_REG 0x17003C
#define CX23888_IR_LEARN_REG 0x170044
#define CX23888_VIDCLK_FREQ 108000000
/* 108 MHz, BT.656 */
#define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
/*
* We use this union internally for convenience, but callers to tx_write
* and rx_read will be expecting records of type struct ir_raw_event.
* Always ensure the size of this union is dictated by struct ir_raw_event.
*/
union cx23888_ir_fifo_rec {
u32 hw_fifo_data;
struct ir_raw_event ir_core_data;
};
#define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
#define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
struct cx23888_ir_state {
struct v4l2_subdev sd;
struct cx23885_dev *dev;
struct v4l2_subdev_ir_parameters rx_params;
struct mutex rx_params_lock;
atomic_t rxclk_divider;
atomic_t rx_invert;
struct kfifo rx_kfifo;
spinlock_t rx_kfifo_lock;
struct v4l2_subdev_ir_parameters tx_params;
struct mutex tx_params_lock;
atomic_t txclk_divider;
};
static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
{
return v4l2_get_subdevdata(sd);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 20 | 100.00% | 1 | 100.00% |
| Total | 20 | 100.00% | 1 | 100.00% |
/*
* IR register block read and write functions
*/
static
inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
{
cx_write(addr, value);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 28 | 100.00% | 2 | 100.00% |
| Total | 28 | 100.00% | 2 | 100.00% |
static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
{
return cx_read(addr);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 21 | 100.00% | 2 | 100.00% |
| Total | 21 | 100.00% | 2 | 100.00% |
static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
u32 and_mask, u32 or_value)
{
cx_andor(addr, ~and_mask, or_value);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 34 | 100.00% | 2 | 100.00% |
| Total | 34 | 100.00% | 2 | 100.00% |
/*
* Rx and Tx Clock Divider register computations
*
* Note the largest clock divider value of 0xffff corresponds to:
* (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
* which fits in 21 bits, so we'll use unsigned int for time arguments.
*/
static inline u16 count_to_clock_divider(unsigned int d)
{
if (d > RXCLK_RCD + 1)
d = RXCLK_RCD;
else if (d < 2)
d = 1;
else
d--;
return (u16) d;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 44 | 100.00% | 2 | 100.00% |
| Total | 44 | 100.00% | 2 | 100.00% |
static inline u16 ns_to_clock_divider(unsigned int ns)
{
return count_to_clock_divider(
DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 26 | 100.00% | 2 | 100.00% |
| Total | 26 | 100.00% | 2 | 100.00% |
static inline unsigned int clock_divider_to_ns(unsigned int divider)
{
/* Period of the Rx or Tx clock in ns */
return DIV_ROUND_CLOSEST((divider + 1) * 1000,
CX23888_IR_REFCLK_FREQ / 1000000);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 29 | 100.00% | 2 | 100.00% |
| Total | 29 | 100.00% | 2 | 100.00% |
static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
{
return count_to_clock_divider(
DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 24 | 100.00% | 1 | 100.00% |
| Total | 24 | 100.00% | 1 | 100.00% |
static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
{
return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 26 | 100.00% | 2 | 100.00% |
| Total | 26 | 100.00% | 2 | 100.00% |
static inline u16 freq_to_clock_divider(unsigned int freq,
unsigned int rollovers)
{
return count_to_clock_divider(
DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 28 | 100.00% | 2 | 100.00% |
| Total | 28 | 100.00% | 2 | 100.00% |
static inline unsigned int clock_divider_to_freq(unsigned int divider,
unsigned int rollovers)
{
return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
(divider + 1) * rollovers);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 30 | 100.00% | 1 | 100.00% |
| Total | 30 | 100.00% | 1 | 100.00% |
/*
* Low Pass Filter register calculations
*
* Note the largest count value of 0xffff corresponds to:
* 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
* which fits in 21 bits, so we'll use unsigned int for time arguments.
*/
static inline u16 count_to_lpf_count(unsigned int d)
{
if (d > FILTR_LPF)
d = FILTR_LPF;
else if (d < 4)
d = 0;
return (u16) d;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 38 | 100.00% | 1 | 100.00% |
| Total | 38 | 100.00% | 1 | 100.00% |
static inline u16 ns_to_lpf_count(unsigned int ns)
{
return count_to_lpf_count(
DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 26 | 100.00% | 1 | 100.00% |
| Total | 26 | 100.00% | 1 | 100.00% |
static inline unsigned int lpf_count_to_ns(unsigned int count)
{
/* Duration of the Low Pass Filter rejection window in ns */
return DIV_ROUND_CLOSEST(count * 1000,
CX23888_IR_REFCLK_FREQ / 1000000);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 25 | 100.00% | 1 | 100.00% |
| Total | 25 | 100.00% | 1 | 100.00% |
static inline unsigned int lpf_count_to_us(unsigned int count)
{
/* Duration of the Low Pass Filter rejection window in us */
return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 23 | 100.00% | 1 | 100.00% |
| Total | 23 | 100.00% | 1 | 100.00% |
/*
* FIFO register pulse width count computations
*/
static u32 clock_divider_to_resolution(u16 divider)
{
/*
* Resolution is the duration of 1 tick of the readable portion of
* of the pulse width counter as read from the FIFO. The two lsb's are
* not readable, hence the << 2. This function returns ns.
*/
return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
CX23888_IR_REFCLK_FREQ / 1000000);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 35 | 100.00% | 1 | 100.00% |
| Total | 35 | 100.00% | 1 | 100.00% |
static u64 pulse_width_count_to_ns(u16 count, u16 divider)
{
u64 n;
u32 rem;
/*
* The 2 lsb's of the pulse width timer count are not readable, hence
* the (count << 2) | 0x3
*/
n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
n++;
return n;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 71 | 100.00% | 1 | 100.00% |
| Total | 71 | 100.00% | 1 | 100.00% |
static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
{
u64 n;
u32 rem;
/*
* The 2 lsb's of the pulse width timer count are not readable, hence
* the (count << 2) | 0x3
*/
n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
n++;
return (unsigned int) n;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 74 | 100.00% | 1 | 100.00% |
| Total | 74 | 100.00% | 1 | 100.00% |
/*
* Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
*
* The total pulse clock count is an 18 bit pulse width timer count as the most
* significant part and (up to) 16 bit clock divider count as a modulus.
* When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
* width timer count's least significant bit.
*/
static u64 ns_to_pulse_clocks(u32 ns)
{
u64 clocks;
u32 rem;
clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
rem = do_div(clocks, 1000); /* /1000 = cycles */
if (rem >= 1000 / 2)
clocks++;
return clocks;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 51 | 100.00% | 2 | 100.00% |
| Total | 51 | 100.00% | 2 | 100.00% |
static u16 pulse_clocks_to_clock_divider(u64 count)
{
do_div(count, (FIFO_RXTX << 2) | 0x3);
/* net result needs to be rounded down and decremented by 1 */
if (count > RXCLK_RCD + 1)
count = RXCLK_RCD;
else if (count < 2)
count = 1;
else
count--;
return (u16) count;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 56 | 100.00% | 1 | 100.00% |
| Total | 56 | 100.00% | 1 | 100.00% |
/*
* IR Control Register helpers
*/
enum tx_fifo_watermark {
TX_FIFO_HALF_EMPTY = 0,
TX_FIFO_EMPTY = CNTRL_TIC,
};
enum rx_fifo_watermark {
RX_FIFO_HALF_FULL = 0,
RX_FIFO_NOT_EMPTY = CNTRL_RIC,
};
static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
enum tx_fifo_watermark level)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 28 | 100.00% | 1 | 100.00% |
| Total | 28 | 100.00% | 1 | 100.00% |
static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
enum rx_fifo_watermark level)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 28 | 100.00% | 1 | 100.00% |
| Total | 28 | 100.00% | 1 | 100.00% |
static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 39 | 100.00% | 1 | 100.00% |
| Total | 39 | 100.00% | 1 | 100.00% |
static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 39 | 100.00% | 1 | 100.00% |
| Total | 39 | 100.00% | 1 | 100.00% |
static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
enable ? CNTRL_MOD : 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 31 | 100.00% | 1 | 100.00% |
| Total | 31 | 100.00% | 1 | 100.00% |
static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
enable ? CNTRL_DMD : 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 31 | 100.00% | 1 | 100.00% |
| Total | 31 | 100.00% | 1 | 100.00% |
static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
u32 edge_types)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
edge_types & CNTRL_EDG_BOTH);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 29 | 100.00% | 1 | 100.00% |
| Total | 29 | 100.00% | 1 | 100.00% |
static void control_rx_s_carrier_window(struct cx23885_dev *dev,
unsigned int carrier,
unsigned int *carrier_range_low,
unsigned int *carrier_range_high)
{
u32 v;
unsigned int c16 = carrier * 16;
if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
v = CNTRL_WIN_3_4;
*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
} else {
v = CNTRL_WIN_3_3;
*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
}
if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
v |= CNTRL_WIN_4_3;
*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
} else {
v |= CNTRL_WIN_3_3;
*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
}
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 150 | 100.00% | 1 | 100.00% |
| Total | 150 | 100.00% | 1 | 100.00% |
static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
bool invert)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
invert ? CNTRL_CPL : 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 31 | 100.00% | 1 | 100.00% |
| Total | 31 | 100.00% | 1 | 100.00% |
static inline void control_tx_level_invert(struct cx23885_dev *dev,
bool invert)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
invert ? CNTRL_IVO : 0);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 31 | 100.00% | 1 | 100.00% |
| Total | 31 | 100.00% | 1 | 100.00% |
/*
* IR Rx & Tx Clock Register helpers
*/
static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
unsigned int freq,
u16 *divider)
{
*divider = carrier_freq_to_clock_divider(freq);
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
return clock_divider_to_carrier_freq(*divider);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 45 | 100.00% | 1 | 100.00% |
| Total | 45 | 100.00% | 1 | 100.00% |
static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
unsigned int freq,
u16 *divider)
{
*divider = carrier_freq_to_clock_divider(freq);
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
return clock_divider_to_carrier_freq(*divider);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 45 | 100.00% | 1 | 100.00% |
| Total | 45 | 100.00% | 1 | 100.00% |
static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
u16 *divider)
{
u64 pulse_clocks;
if (ns > IR_MAX_DURATION)
ns = IR_MAX_DURATION;
pulse_clocks = ns_to_pulse_clocks(ns);
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 68 | 100.00% | 2 | 100.00% |
| Total | 68 | 100.00% | 2 | 100.00% |
static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
u16 *divider)
{
u64 pulse_clocks;
if (ns > IR_MAX_DURATION)
ns = IR_MAX_DURATION;
pulse_clocks = ns_to_pulse_clocks(ns);
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 68 | 100.00% | 2 | 100.00% |
| Total | 68 | 100.00% | 2 | 100.00% |
/*
* IR Tx Carrier Duty Cycle register helpers
*/
static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
unsigned int duty_cycle)
{
u32 n;
n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
if (n != 0)
n--;
if (n > 15)
n = 15;
cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 73 | 100.00% | 1 | 100.00% |
| Total | 73 | 100.00% | 1 | 100.00% |
/*
* IR Filter Register helpers
*/
static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
{
u32 count = ns_to_lpf_count(min_width_ns);
cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
return lpf_count_to_ns(count);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 37 | 100.00% | 1 | 100.00% |
| Total | 37 | 100.00% | 1 | 100.00% |
/*
* IR IRQ Enable Register helpers
*/
static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
{
mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 43 | 100.00% | 1 | 100.00% |
| Total | 43 | 100.00% | 1 | 100.00% |
static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
{
mask &= IRQEN_TSE;
cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 31 | 100.00% | 1 | 100.00% |
| Total | 31 | 100.00% | 1 | 100.00% |
/*
* V4L2 Subdevice IR Ops
*/
static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
bool *handled)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
unsigned long flags;
u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
unsigned int i, j, k;
u32 events, v;
int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
ror = stats & STATS_ROR; /* Rx FIFO Over Run */
tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
*handled = false;
v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
tsr ? "tsr" : " ", rsr ? "rsr" : " ",
rto ? "rto" : " ", ror ? "ror" : " ",
stats & STATS_TBY ? "tby" : " ",
stats & STATS_RBY ? "rby" : " ");
v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
tse ? "tse" : " ", rse ? "rse" : " ",
rte ? "rte" : " ", roe ? "roe" : " ");
/*
* Transmitter interrupt service
*/
if (tse && tsr) {
/*
* TODO:
* Check the watermark threshold setting
* Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
* Push the data to the hardware FIFO.
* If there was nothing more to send in the tx_kfifo, disable
* the TSR IRQ and notify the v4l2_device.
* If there was something in the tx_kfifo, check the tx_kfifo
* level and notify the v4l2_device, if it is low.
*/
/* For now, inhibit TSR interrupt until Tx is implemented */
irqenable_tx(dev, 0);
events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
*handled = true;
}
/*
* Receiver interrupt service
*/
kror = 0;
if ((rse && rsr) || (rte && rto)) {
/*
* Receive data on RSR to clear the STATS_RSR.
* Receive data on RTO, since we may not have yet hit the RSR
* watermark when we receive the RTO.
*/
for (i = 0, v = FIFO_RX_NDV;
(v & FIFO_RX_NDV) && !kror; i = 0) {
for (j = 0;
(v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
i++;
}
if (i == 0)
break;
j = i * sizeof(union cx23888_ir_fifo_rec);
k = kfifo_in_locked(&state->rx_kfifo,
(unsigned char *) rx_data, j,
&state->rx_kfifo_lock);
if (k != j)
kror++; /* rx_kfifo over run */
}
*handled = true;
}
events = 0;
v = 0;
if (kror) {
events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
v4l2_err(sd, "IR receiver software FIFO overrun\n");
}
if (roe && ror) {
/*
* The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
* the Rx FIFO Over Run status (STATS_ROR)
*/
v |= CNTRL_RFE;
events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
}
if (rte && rto) {
/*
* The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
* the Rx Pulse Width Timer Time Out (STATS_RTO)
*/
v |= CNTRL_RXE;
events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
}
if (v) {
/* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
*handled = true;
}
spin_lock_irqsave(&state->rx_kfifo_lock, flags);
if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
if (events)
v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 564 | 94.63% | 2 | 66.67% |
| stefani seibold | stefani seibold | 32 | 5.37% | 1 | 33.33% |
| Total | 596 | 100.00% | 3 | 100.00% |
/* Receiver */
static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
ssize_t *num)
{
struct cx23888_ir_state *state = to_state(sd);
bool invert = (bool) atomic_read(&state->rx_invert);
u16 divider = (u16) atomic_read(&state->rxclk_divider);
unsigned int i, n;
union cx23888_ir_fifo_rec *p;
unsigned u, v, w;
n = count / sizeof(union cx23888_ir_fifo_rec)
* sizeof(union cx23888_ir_fifo_rec);
if (n == 0) {
*num = 0;
return 0;
}
n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
n /= sizeof(union cx23888_ir_fifo_rec);
*num = n * sizeof(union cx23888_ir_fifo_rec);
for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
/* Assume RTO was because of no IR light input */
u = 0;
w = 1;
} else {
u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
if (invert)
u = u ? 0 : 1;
w = 0;
}
v = (unsigned) pulse_width_count_to_ns(
(u16) (p->hw_fifo_data & FIFO_RXTX), divider);
if (v > IR_MAX_DURATION)
v = IR_MAX_DURATION;
init_ir_raw_event(&p->ir_core_data);
p->ir_core_data.pulse = u;
p->ir_core_data.duration = v;
p->ir_core_data.timeout = w;
v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n",
v, u ? "mark" : "space", w ? "(timed out)" : "");
if (w)
v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
}
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 322 | 95.55% | 4 | 66.67% |
| maxim levitsky | maxim levitsky | 8 | 2.37% | 1 | 16.67% |
| stefani seibold | stefani seibold | 7 | 2.08% | 1 | 16.67% |
| Total | 337 | 100.00% | 6 | 100.00% |
static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
mutex_lock(&state->rx_params_lock);
memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
mutex_unlock(&state->rx_params_lock);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 61 | 100.00% | 1 | 100.00% |
| Total | 61 | 100.00% | 1 | 100.00% |
static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
mutex_lock(&state->rx_params_lock);
/* Disable or slow down all IR Rx circuits and counters */
irqenable_rx(dev, 0);
control_rx_enable(dev, false);
control_rx_demodulation_enable(dev, false);
control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
filter_rx_s_min_width(dev, 0);
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
state->rx_params.shutdown = true;
mutex_unlock(&state->rx_params_lock);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 102 | 100.00% | 1 | 100.00% |
| Total | 102 | 100.00% | 1 | 100.00% |
static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
struct v4l2_subdev_ir_parameters *o = &state->rx_params;
u16 rxclk_divider;
if (p->shutdown)
return cx23888_ir_rx_shutdown(sd);
if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
return -ENOSYS;
mutex_lock(&state->rx_params_lock);
o->shutdown = p->shutdown;
o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
o->bytes_per_data_element = p->bytes_per_data_element
= sizeof(union cx23888_ir_fifo_rec);
/* Before we tweak the hardware, we have to disable the receiver */
irqenable_rx(dev, 0);
control_rx_enable(dev, false);
control_rx_demodulation_enable(dev, p->modulation);
o->modulation = p->modulation;
if (p->modulation) {
p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
&rxclk_divider);
o->carrier_freq = p->carrier_freq;
o->duty_cycle = p->duty_cycle = 50;
control_rx_s_carrier_window(dev, p->carrier_freq,
&p->carrier_range_lower,
&p->carrier_range_upper);
o->carrier_range_lower = p->carrier_range_lower;
o->carrier_range_upper = p->carrier_range_upper;
p->max_pulse_width =
(u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
} else {
p->max_pulse_width =
rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
&rxclk_divider);
}
o->max_pulse_width = p->max_pulse_width;
atomic_set(&state->rxclk_divider, rxclk_divider);
p->noise_filter_min_width =
filter_rx_s_min_width(dev, p->noise_filter_min_width);
o->noise_filter_min_width = p->noise_filter_min_width;
p->resolution = clock_divider_to_resolution(rxclk_divider);
o->resolution = p->resolution;
/* FIXME - make this dependent on resolution for better performance */
control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
o->invert_level = p->invert_level;
atomic_set(&state->rx_invert, p->invert_level);
o->interrupt_enable = p->interrupt_enable;
o->enable = p->enable;
if (p->enable) {
unsigned long flags;
spin_lock_irqsave(&state->rx_kfifo_lock, flags);
kfifo_reset(&state->rx_kfifo);
/* reset tx_fifo too if there is one... */
spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
if (p->interrupt_enable)
irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
control_rx_enable(dev, p->enable);
}
mutex_unlock(&state->rx_params_lock);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 413 | 94.08% | 4 | 80.00% |
| stefani seibold | stefani seibold | 26 | 5.92% | 1 | 20.00% |
| Total | 439 | 100.00% | 5 | 100.00% |
/* Transmitter */
static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
ssize_t *num)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
/* For now enable the Tx FIFO Service interrupt & pretend we did work */
irqenable_tx(dev, IRQEN_TSE);
*num = count;
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 57 | 100.00% | 1 | 100.00% |
| Total | 57 | 100.00% | 1 | 100.00% |
static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
mutex_lock(&state->tx_params_lock);
memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
mutex_unlock(&state->tx_params_lock);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 61 | 100.00% | 1 | 100.00% |
| Total | 61 | 100.00% | 1 | 100.00% |
static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
mutex_lock(&state->tx_params_lock);
/* Disable or slow down all IR Tx circuits and counters */
irqenable_tx(dev, 0);
control_tx_enable(dev, false);
control_tx_modulation_enable(dev, false);
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
state->tx_params.shutdown = true;
mutex_unlock(&state->tx_params_lock);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 88 | 100.00% | 1 | 100.00% |
| Total | 88 | 100.00% | 1 | 100.00% |
static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
struct v4l2_subdev_ir_parameters *o = &state->tx_params;
u16 txclk_divider;
if (p->shutdown)
return cx23888_ir_tx_shutdown(sd);
if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
return -ENOSYS;
mutex_lock(&state->tx_params_lock);
o->shutdown = p->shutdown;
o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
o->bytes_per_data_element = p->bytes_per_data_element
= sizeof(union cx23888_ir_fifo_rec);
/* Before we tweak the hardware, we have to disable the transmitter */
irqenable_tx(dev, 0);
control_tx_enable(dev, false);
control_tx_modulation_enable(dev, p->modulation);
o->modulation = p->modulation;
if (p->modulation) {
p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
&txclk_divider);
o->carrier_freq = p->carrier_freq;
p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
o->duty_cycle = p->duty_cycle;
p->max_pulse_width =
(u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
} else {
p->max_pulse_width =
txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
&txclk_divider);
}
o->max_pulse_width = p->max_pulse_width;
atomic_set(&state->txclk_divider, txclk_divider);
p->resolution = clock_divider_to_resolution(txclk_divider);
o->resolution = p->resolution;
/* FIXME - make this dependent on resolution for better performance */
control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
control_tx_polarity_invert(dev, p->invert_carrier_sense);
o->invert_carrier_sense = p->invert_carrier_sense;
control_tx_level_invert(dev, p->invert_level);
o->invert_level = p->invert_level;
o->interrupt_enable = p->interrupt_enable;
o->enable = p->enable;
if (p->enable) {
if (p->interrupt_enable)
irqenable_tx(dev, IRQEN_TSE);
control_tx_enable(dev, p->enable);
}
mutex_unlock(&state->tx_params_lock);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 364 | 100.00% | 4 | 100.00% |
| Total | 364 | 100.00% | 4 | 100.00% |
/*
* V4L2 Subdevice Core Ops
*/
static int cx23888_ir_log_status(struct v4l2_subdev *sd)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
char *s;
int i, j;
u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
v4l2_info(sd, "IR Receiver:\n");
v4l2_info(sd, "\tEnabled: %s\n",
cntrl & CNTRL_RXE ? "yes" : "no");
v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
cntrl & CNTRL_DMD ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO: %s\n",
cntrl & CNTRL_RFE ? "enabled" : "disabled");
switch (cntrl & CNTRL_EDG) {
case CNTRL_EDG_NONE:
s = "disabled";
break;
case CNTRL_EDG_FALL:
s = "falling edge";
break;
case CNTRL_EDG_RISE:
s = "rising edge";
break;
case CNTRL_EDG_BOTH:
s = "rising & falling edges";
break;
default:
s = "??? edge";
break;
}
v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
cntrl & CNTRL_R ? "not loaded" : "overflow marker");
v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
v4l2_info(sd, "\tLoopback mode: %s\n",
cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
if (cntrl & CNTRL_DMD) {
v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
clock_divider_to_carrier_freq(rxclk));
switch (cntrl & CNTRL_WIN) {
case CNTRL_WIN_3_3:
i = 3;
j = 3;
break;
case CNTRL_WIN_4_3:
i = 4;
j = 3;
break;
case CNTRL_WIN_3_4:
i = 3;
j = 4;
break;
case CNTRL_WIN_4_4:
i = 4;
j = 4;
break;
default:
i = 0;
j = 0;
break;
}
v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
"-%1d/+%1d, %u to %u Hz\n", i, j,
clock_divider_to_freq(rxclk, 16 + j),
clock_divider_to_freq(rxclk, 16 - i));
}
v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
pulse_width_count_to_us(FIFO_RXTX, rxclk),
pulse_width_count_to_ns(FIFO_RXTX, rxclk));
v4l2_info(sd, "\tLow pass filter: %s\n",
filtr ? "enabled" : "disabled");
if (filtr)
v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
"%u ns\n",
lpf_count_to_us(filtr),
lpf_count_to_ns(filtr));
v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
stats & STATS_RTO ? "yes" : "no");
v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
irqen & IRQEN_RTE ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO overrun: %s\n",
stats & STATS_ROR ? "yes" : "no");
v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
irqen & IRQEN_ROE ? "enabled" : "disabled");
v4l2_info(sd, "\tBusy: %s\n",
stats & STATS_RBY ? "yes" : "no");
v4l2_info(sd, "\tFIFO service requested: %s\n",
stats & STATS_RSR ? "yes" : "no");
v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
irqen & IRQEN_RSE ? "enabled" : "disabled");
v4l2_info(sd, "IR Transmitter:\n");
v4l2_info(sd, "\tEnabled: %s\n",
cntrl & CNTRL_TXE ? "yes" : "no");
v4l2_info(sd, "\tModulation onto a carrier: %s\n",
cntrl & CNTRL_MOD ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO: %s\n",
cntrl & CNTRL_TFE ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
cntrl & CNTRL_TIC ? "not empty" : "half full or less");
v4l2_info(sd, "\tOutput pin level inversion %s\n",
cntrl & CNTRL_IVO ? "yes" : "no");
v4l2_info(sd, "\tCarrier polarity: %s\n",
cntrl & CNTRL_CPL ? "space:burst mark:noburst"
: "space:noburst mark:burst");
if (cntrl & CNTRL_MOD) {
v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
clock_divider_to_carrier_freq(txclk));
v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
cduty + 1);
}
v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
pulse_width_count_to_us(FIFO_RXTX, txclk),
pulse_width_count_to_ns(FIFO_RXTX, txclk));
v4l2_info(sd, "\tBusy: %s\n",
stats & STATS_TBY ? "yes" : "no");
v4l2_info(sd, "\tFIFO service requested: %s\n",
stats & STATS_TSR ? "yes" : "no");
v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
irqen & IRQEN_TSE ? "enabled" : "disabled");
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 743 | 100.00% | 4 | 100.00% |
| Total | 743 | 100.00% | 4 | 100.00% |
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int cx23888_ir_g_register(struct v4l2_subdev *sd,
struct v4l2_dbg_register *reg)
{
struct cx23888_ir_state *state = to_state(sd);
u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
if ((addr & 0x3) != 0)
return -EINVAL;
if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
return -EINVAL;
reg->size = 4;
reg->val = cx23888_ir_read4(state->dev, addr);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 88 | 100.00% | 1 | 100.00% |
| Total | 88 | 100.00% | 1 | 100.00% |
static int cx23888_ir_s_register(struct v4l2_subdev *sd,
const struct v4l2_dbg_register *reg)
{
struct cx23888_ir_state *state = to_state(sd);
u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
if ((addr & 0x3) != 0)
return -EINVAL;
if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
return -EINVAL;
cx23888_ir_write4(state->dev, addr, reg->val);
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 82 | 98.80% | 1 | 50.00% |
| hans verkuil | hans verkuil | 1 | 1.20% | 1 | 50.00% |
| Total | 83 | 100.00% | 2 | 100.00% |
#endif
static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
.log_status = cx23888_ir_log_status,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.g_register = cx23888_ir_g_register,
.s_register = cx23888_ir_s_register,
#endif
.interrupt_service_routine = cx23888_ir_irq_handler,
};
static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
.rx_read = cx23888_ir_rx_read,
.rx_g_parameters = cx23888_ir_rx_g_parameters,
.rx_s_parameters = cx23888_ir_rx_s_parameters,
.tx_write = cx23888_ir_tx_write,
.tx_g_parameters = cx23888_ir_tx_g_parameters,
.tx_s_parameters = cx23888_ir_tx_s_parameters,
};
static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
.core = &cx23888_ir_core_ops,
.ir = &cx23888_ir_ir_ops,
};
static const struct v4l2_subdev_ir_parameters default_rx_params = {
.bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
.enable = false,
.interrupt_enable = false,
.shutdown = true,
.modulation = true,
.carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
/* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
/* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
.noise_filter_min_width = 333333, /* ns */
.carrier_range_lower = 35000,
.carrier_range_upper = 37000,
.invert_level = false,
};
static const struct v4l2_subdev_ir_parameters default_tx_params = {
.bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
.enable = false,
.interrupt_enable = false,
.shutdown = true,
.modulation = true,
.carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
.duty_cycle = 25, /* 25 % - RC-5 carrier */
.invert_level = false,
.invert_carrier_sense = false,
};
int cx23888_ir_probe(struct cx23885_dev *dev)
{
struct cx23888_ir_state *state;
struct v4l2_subdev *sd;
struct v4l2_subdev_ir_parameters default_params;
int ret;
state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;
spin_lock_init(&state->rx_kfifo_lock);
if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
return -ENOMEM;
state->dev = dev;
sd = &state->sd;
v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
v4l2_set_subdevdata(sd, state);
/* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
sd->grp_id = CX23885_HW_888_IR;
ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
if (ret == 0) {
/*
* Ensure no interrupts arrive from '888 specific conditions,
* since we ignore them in this driver to have commonality with
* similar IR controller cores.
*/
cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
mutex_init(&state->rx_params_lock);
default_params = default_rx_params;
v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
mutex_init(&state->tx_params_lock);
default_params = default_tx_params;
v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
} else {
kfifo_free(&state->rx_kfifo);
}
return ret;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 216 | 96.86% | 2 | 50.00% |
| stefani seibold | stefani seibold | 5 | 2.24% | 1 | 25.00% |
| ezequiel garcia | ezequiel garcia | 2 | 0.90% | 1 | 25.00% |
| Total | 223 | 100.00% | 4 | 100.00% |
int cx23888_ir_remove(struct cx23885_dev *dev)
{
struct v4l2_subdev *sd;
struct cx23888_ir_state *state;
sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
if (sd == NULL)
return -ENODEV;
cx23888_ir_rx_shutdown(sd);
cx23888_ir_tx_shutdown(sd);
state = to_state(sd);
v4l2_device_unregister_subdev(sd);
kfifo_free(&state->rx_kfifo);
kfree(state);
/* Nothing more to free() as state held the actual v4l2_subdev object */
return 0;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 77 | 98.72% | 2 | 66.67% |
| stefani seibold | stefani seibold | 1 | 1.28% | 1 | 33.33% |
| Total | 78 | 100.00% | 3 | 100.00% |
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| andy walls | andy walls | 5418 | 98.35% | 9 | 50.00% |
| stefani seibold | stefani seibold | 71 | 1.29% | 1 | 5.56% |
| maxim levitsky | maxim levitsky | 8 | 0.15% | 1 | 5.56% |
| mauro carvalho chehab | mauro carvalho chehab | 4 | 0.07% | 2 | 11.11% |
| tejun heo | tejun heo | 3 | 0.05% | 1 | 5.56% |
| hans verkuil | hans verkuil | 2 | 0.04% | 2 | 11.11% |
| ezequiel garcia | ezequiel garcia | 2 | 0.04% | 1 | 5.56% |
| geert uytterhoeven | geert uytterhoeven | 1 | 0.02% | 1 | 5.56% |
| Total | 5509 | 100.00% | 18 | 100.00% |
Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.