/* * IMX pinmux core definitions * * Copyright (C) 2012 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. * * Author: Dong Aisheng <dong.aisheng@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #ifndef __DRIVERS_PINCTRL_IMX_H #define __DRIVERS_PINCTRL_IMX_H struct platform_device; /** * struct imx_pin_group - describes a single i.MX pin * @pin: the pin_id of this pin * @mux_mode: the mux mode for this pin. * @input_reg: the select input register offset for this pin if any * 0 if no select input setting needed. * @input_val: the select input value for this pin. * @configs: the config for this pin. */ struct imx_pin { unsigned int pin; unsigned int mux_mode; u16 input_reg; unsigned int input_val; unsigned long config; }; /** * struct imx_pin_group - describes an IMX pin group * @name: the name of this specific pin group * @npins: the number of pins in this group array, i.e. the number of * elements in .pins so we can iterate over that array * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array * @pins: array of pins */ struct imx_pin_group { const char *name; unsigned npins; unsigned int *pin_ids; struct imx_pin *pins; }; /** * struct imx_pmx_func - describes IMX pinmux functions * @name: the name of this specific function * @groups: corresponding pin groups * @num_groups: the number of groups */ struct imx_pmx_func { const char *name; const char **groups; unsigned num_groups; }; /** * struct imx_pin_reg - describe a pin reg map * @mux_reg: mux register offset * @conf_reg: config register offset */ struct imx_pin_reg { s16 mux_reg; s16 conf_reg; }; struct imx_pinctrl_soc_info { struct device *dev; const struct pinctrl_pin_desc *pins; unsigned int npins; struct imx_pin_reg *pin_regs; struct imx_pin_group *groups; unsigned int ngroups; unsigned int group_index; struct imx_pmx_func *functions; unsigned int nfunctions; unsigned int flags; const char *gpr_compatible; }; #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 #define NO_MUX 0x0 #define NO_PAD 0x0 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) #define PAD_CTL_MASK(len) ((1 << len) - 1) #define IMX_MUX_MASK 0x7 #define IOMUXC_CONFIG_SION (0x1 << 4) int imx_pinctrl_probe(struct platform_device *pdev, struct imx_pinctrl_soc_info *info); #endif /* __DRIVERS_PINCTRL_IMX_H */Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp | |
| dong aisheng | dong aisheng | 144 | 71.29% | 1 | 12.50% |
| sascha hauer | sascha hauer | 27 | 13.37% | 1 | 12.50% |
| shawn guo | shawn guo | 8 | 3.96% | 1 | 12.50% |
| jingchang lu | jingchang lu | 7 | 3.47% | 1 | 12.50% |
| philipp zabel | philipp zabel | 5 | 2.48% | 1 | 12.50% |
| robin gong | robin gong | 4 | 1.98% | 1 | 12.50% |
| adrian alonso | adrian alonso | 4 | 1.98% | 1 | 12.50% |
| stefan agner | stefan agner | 3 | 1.49% | 1 | 12.50% |
| Total | 202 | 100.00% | 8 | 100.00% |