Release 4.7 include/dt-bindings/clock/bcm-nsp.h

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above copyright
 *        notice, this list of conditions and the following disclaimer in
 *        the documentation and/or other materials provided with the
 *        distribution.
 *      * Neither the name of Broadcom Corporation nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _CLOCK_BCM_NSP_H

#define _CLOCK_BCM_NSP_H

/* GENPLL clock channel ID */

#define BCM_NSP_GENPLL			0

#define BCM_NSP_GENPLL_PHY_CLK		1

#define BCM_NSP_GENPLL_ENET_SW_CLK	2

#define BCM_NSP_GENPLL_USB_PHY_REF_CLK	3

#define BCM_NSP_GENPLL_IPROCFAST_CLK	4

#define BCM_NSP_GENPLL_SATA1_CLK	5

#define BCM_NSP_GENPLL_SATA2_CLK	6

/* LCPLL0 clock channel ID */

#define BCM_NSP_LCPLL0			0

#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK	1

#define BCM_NSP_LCPLL0_SDIO_CLK		2

#define BCM_NSP_LCPLL0_DDR_PHY_CLK	3

#endif /* _CLOCK_BCM_NSP_H */
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Directory: include/dt-bindings/clock

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