Release 4.7 include/soc/tegra/pmc.h
/*
* Copyright (c) 2010 Google, Inc
* Copyright (c) 2014 NVIDIA Corporation
*
* Author:
* Colin Cross <ccross@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SOC_TEGRA_PMC_H__
#define __SOC_TEGRA_PMC_H__
#include <linux/reboot.h>
#include <soc/tegra/pm.h>
struct clk;
struct reset_control;
#ifdef CONFIG_PM_SLEEP
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
#endif /* CONFIG_PM_SLEEP */
#ifdef CONFIG_SMP
bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
int tegra_pmc_cpu_power_on(unsigned int cpuid);
int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
#endif /* CONFIG_SMP */
/*
* powergate and I/O rail APIs
*/
#define TEGRA_POWERGATE_CPU 0
#define TEGRA_POWERGATE_3D 1
#define TEGRA_POWERGATE_VENC 2
#define TEGRA_POWERGATE_PCIE 3
#define TEGRA_POWERGATE_VDEC 4
#define TEGRA_POWERGATE_L2 5
#define TEGRA_POWERGATE_MPE 6
#define TEGRA_POWERGATE_HEG 7
#define TEGRA_POWERGATE_SATA 8
#define TEGRA_POWERGATE_CPU1 9
#define TEGRA_POWERGATE_CPU2 10
#define TEGRA_POWERGATE_CPU3 11
#define TEGRA_POWERGATE_CELP 12
#define TEGRA_POWERGATE_3D1 13
#define TEGRA_POWERGATE_CPU0 14
#define TEGRA_POWERGATE_C0NC 15
#define TEGRA_POWERGATE_C1NC 16
#define TEGRA_POWERGATE_SOR 17
#define TEGRA_POWERGATE_DIS 18
#define TEGRA_POWERGATE_DISB 19
#define TEGRA_POWERGATE_XUSBA 20
#define TEGRA_POWERGATE_XUSBB 21
#define TEGRA_POWERGATE_XUSBC 22
#define TEGRA_POWERGATE_VIC 23
#define TEGRA_POWERGATE_IRAM 24
#define TEGRA_POWERGATE_NVDEC 25
#define TEGRA_POWERGATE_NVJPG 26
#define TEGRA_POWERGATE_AUD 27
#define TEGRA_POWERGATE_DFD 28
#define TEGRA_POWERGATE_VE2 29
#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
#define TEGRA_IO_RAIL_CSIA 0
#define TEGRA_IO_RAIL_CSIB 1
#define TEGRA_IO_RAIL_DSI 2
#define TEGRA_IO_RAIL_MIPI_BIAS 3
#define TEGRA_IO_RAIL_PEX_BIAS 4
#define TEGRA_IO_RAIL_PEX_CLK1 5
#define TEGRA_IO_RAIL_PEX_CLK2 6
#define TEGRA_IO_RAIL_USB0 9
#define TEGRA_IO_RAIL_USB1 10
#define TEGRA_IO_RAIL_USB2 11
#define TEGRA_IO_RAIL_USB_BIAS 12
#define TEGRA_IO_RAIL_NAND 13
#define TEGRA_IO_RAIL_UART 14
#define TEGRA_IO_RAIL_BB 15
#define TEGRA_IO_RAIL_AUDIO 17
#define TEGRA_IO_RAIL_HSIC 19
#define TEGRA_IO_RAIL_COMP 22
#define TEGRA_IO_RAIL_HDMI 28
#define TEGRA_IO_RAIL_PEX_CNTRL 32
#define TEGRA_IO_RAIL_SDMMC1 33
#define TEGRA_IO_RAIL_SDMMC3 34
#define TEGRA_IO_RAIL_SDMMC4 35
#define TEGRA_IO_RAIL_CAM 36
#define TEGRA_IO_RAIL_RES 37
#define TEGRA_IO_RAIL_HV 38
#define TEGRA_IO_RAIL_DSIB 39
#define TEGRA_IO_RAIL_DSIC 40
#define TEGRA_IO_RAIL_DSID 41
#define TEGRA_IO_RAIL_CSIE 44
#define TEGRA_IO_RAIL_LVDS 57
#define TEGRA_IO_RAIL_SYS_DDC 58
#ifdef CONFIG_ARCH_TEGRA
int tegra_powergate_is_powered(unsigned int id);
int tegra_powergate_power_on(unsigned int id);
int tegra_powergate_power_off(unsigned int id);
int tegra_powergate_remove_clamping(unsigned int id);
/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
struct reset_control *rst);
int tegra_io_rail_power_on(unsigned int id);
int tegra_io_rail_power_off(unsigned int id);
#else
static inline int tegra_powergate_is_powered(unsigned int id)
{
return -ENOSYS;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 14 | 93.33% | 1 | 50.00% |
| jon hunter | jon hunter | 1 | 6.67% | 1 | 50.00% |
| Total | 15 | 100.00% | 2 | 100.00% |
static inline int tegra_powergate_power_on(unsigned int id)
{
return -ENOSYS;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 14 | 93.33% | 1 | 50.00% |
| jon hunter | jon hunter | 1 | 6.67% | 1 | 50.00% |
| Total | 15 | 100.00% | 2 | 100.00% |
static inline int tegra_powergate_power_off(unsigned int id)
{
return -ENOSYS;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 14 | 93.33% | 1 | 50.00% |
| jon hunter | jon hunter | 1 | 6.67% | 1 | 50.00% |
| Total | 15 | 100.00% | 2 | 100.00% |
static inline int tegra_powergate_remove_clamping(unsigned int id)
{
return -ENOSYS;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 14 | 93.33% | 1 | 50.00% |
| jon hunter | jon hunter | 1 | 6.67% | 1 | 50.00% |
| Total | 15 | 100.00% | 2 | 100.00% |
static inline int tegra_powergate_sequence_power_up(unsigned int id,
struct clk *clk,
struct reset_control *rst)
{
return -ENOSYS;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 19 | 76.00% | 1 | 33.33% |
| stephen warren | stephen warren | 5 | 20.00% | 1 | 33.33% |
| jon hunter | jon hunter | 1 | 4.00% | 1 | 33.33% |
| Total | 25 | 100.00% | 3 | 100.00% |
static inline int tegra_io_rail_power_on(unsigned int id)
{
return -ENOSYS;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 14 | 93.33% | 1 | 50.00% |
| jon hunter | jon hunter | 1 | 6.67% | 1 | 50.00% |
| Total | 15 | 100.00% | 2 | 100.00% |
static inline int tegra_io_rail_power_off(unsigned int id)
{
return -ENOSYS;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 14 | 93.33% | 1 | 50.00% |
| jon hunter | jon hunter | 1 | 6.67% | 1 | 50.00% |
| Total | 15 | 100.00% | 2 | 100.00% |
#endif /* CONFIG_ARCH_TEGRA */
#endif /* __SOC_TEGRA_PMC_H__ */
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| thierry reding | thierry reding | 377 | 71.95% | 6 | 46.15% |
| colin cross | colin cross | 68 | 12.98% | 1 | 7.69% |
| peter de schrijver | peter de schrijver | 42 | 8.02% | 2 | 15.38% |
| jon hunter | jon hunter | 21 | 4.01% | 2 | 15.38% |
| stephen warren | stephen warren | 16 | 3.05% | 2 | 15.38% |
| Total | 524 | 100.00% | 13 | 100.00% |
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