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Release 4.8 sound/drivers/ml403-ac97cr.c

Directory: sound/drivers
/*
 * ALSA driver for Xilinx ML403 AC97 Controller Reference
 *   IP: opb_ac97_controller_ref_v1_00_a (EDK 8.1i)
 *   IP: opb_ac97_controller_ref_v1_00_a (EDK 9.1i)
 *
 *  Copyright (c) by 2007  Joachim Foerster <JOFT@gmx.de>
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

/* Some notes / status of this driver:
 *
 * - Don't wonder about some strange implementations of things - especially the
 * (heavy) shadowing of codec registers, with which I tried to reduce read
 * accesses to a minimum, because after a variable amount of accesses, the AC97
 * controller doesn't raise the register access finished bit anymore ...
 *
 * - Playback support seems to be pretty stable - no issues here.
 * - Capture support "works" now, too. Overruns don't happen any longer so often.
 *   But there might still be some ...
 */

#include <linux/init.h>
#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/interrupt.h>

/* HZ */
#include <linux/param.h>
/* jiffies, time_*() */
#include <linux/jiffies.h>
/* schedule_timeout*() */
#include <linux/sched.h>
/* spin_lock*() */
#include <linux/spinlock.h>
/* struct mutex, mutex_init(), mutex_*lock() */
#include <linux/mutex.h>

/* snd_printk(), snd_printd() */
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/ac97_codec.h>

#include "pcm-indirect2.h"



#define SND_ML403_AC97CR_DRIVER "ml403-ac97cr"

MODULE_AUTHOR("Joachim Foerster <JOFT@gmx.de>");
MODULE_DESCRIPTION("Xilinx ML403 AC97 Controller Reference");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Xilinx,ML403 AC97 Controller Reference}}");


static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;

static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;

static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE;

module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for ML403 AC97 Controller Reference.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for ML403 AC97 Controller Reference.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable this ML403 AC97 Controller Reference.");

/* Special feature options */
/*#define CODEC_WRITE_CHECK_RAF*/ /* don't return after a write to a codec
                                   * register, while RAF bit is not set
                                   */
/* Debug options for code which may be removed completely in a final version */
#ifdef CONFIG_SND_DEBUG
/*#define CODEC_STAT*/            /* turn on some minimal "statistics"
                                   * about codec register usage
                                   */

#define SND_PCM_INDIRECT2_STAT    
/* turn on some "statistics" about the
                                   * process of copying bytes from the
                                   * intermediate buffer to the hardware
                                   * fifo and the other way round
                                   */
#endif

/* Definition of a "level/facility dependent" printk(); may be removed
 * completely in a final version
 */

#undef PDEBUG
#ifdef CONFIG_SND_DEBUG
/* "facilities" for PDEBUG */

#define UNKNOWN       (1<<0)

#define CODEC_SUCCESS (1<<1)

#define CODEC_FAKE    (1<<2)

#define INIT_INFO     (1<<3)

#define INIT_FAILURE  (1<<4)

#define WORK_INFO     (1<<5)

#define WORK_FAILURE  (1<<6)


#define PDEBUG_FACILITIES (UNKNOWN | INIT_FAILURE | WORK_FAILURE)


#define PDEBUG(fac, fmt, args...) do { \
                if (fac & PDEBUG_FACILITIES) \
                        snd_printd(KERN_DEBUG SND_ML403_AC97CR_DRIVER ": " \
                                   fmt, ##args); \
        } while (0)
#else

#define PDEBUG(fac, fmt, args...) 
/* nothing */
#endif



/* Defines for "waits"/timeouts (portions of HZ=250 on arch/ppc by default) */

#define CODEC_TIMEOUT_ON_INIT       5	
/* timeout for checking for codec
                                         * readiness (after insmod)
                                         */
#ifndef CODEC_WRITE_CHECK_RAF

#define CODEC_WAIT_AFTER_WRITE    100	
/* general, static wait after a write
                                         * access to a codec register, may be
                                         * 0 to completely remove wait
                                         */
#else

#define CODEC_TIMEOUT_AFTER_WRITE   5	
/* timeout after a write access to a
                                         * codec register, if RAF bit is used
                                         */
#endif

#define CODEC_TIMEOUT_AFTER_READ    5	
/* timeout after a read access to a
                                         * codec register (checking RAF bit)
                                         */

/* Infrastructure for codec register shadowing */

#define LM4550_REG_OK        (1<<0)   
/* register exists */

#define LM4550_REG_DONEREAD  (1<<1)   
/* read register once, value should be
                                       * the same currently in the register
                                       */

#define LM4550_REG_NOSAVE    (1<<2)   
/* values written to this register will
                                       * not be saved in the register
                                       */

#define LM4550_REG_NOSHADOW  (1<<3)   
/* don't do register shadowing, use plain
                                       * hardware access
                                       */

#define LM4550_REG_READONLY  (1<<4)   
/* register is read only */

#define LM4550_REG_FAKEPROBE (1<<5)   
/* fake write _and_ read actions during
                                       * probe() correctly
                                       */

#define LM4550_REG_FAKEREAD  (1<<6)   
/* fake read access, always return
                                       * default value
                                       */

#define LM4550_REG_ALLFAKE   (LM4550_REG_FAKEREAD | LM4550_REG_FAKEPROBE)


struct lm4550_reg {
	
u16 value;
	
u16 flag;
	
u16 wmask;
	
u16 def;
};


struct lm4550_reg lm4550_regfile[64] = {
	[AC97_RESET / 2]              = {.flag = LM4550_REG_OK \
						| LM4550_REG_NOSAVE \
						| LM4550_REG_FAKEREAD,
					 .def = 0x0D50},
	[AC97_MASTER / 2]             = {.flag = LM4550_REG_OK
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x9F1F,
					 .def = 0x8000},
	[AC97_HEADPHONE / 2]          = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x9F1F,
					 .def = 0x8000},
	[AC97_MASTER_MONO / 2]        = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x801F,
					 .def = 0x8000},
	[AC97_PC_BEEP / 2]            = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x801E,
					 .def = 0x0},
	[AC97_PHONE / 2]              = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x801F,
					 .def = 0x8008},
	[AC97_MIC / 2]                = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x805F,
					 .def = 0x8008},
	[AC97_LINE / 2]               = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x9F1F,
					 .def = 0x8808},
	[AC97_CD / 2]                 = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x9F1F,
					 .def = 0x8808},
	[AC97_VIDEO / 2]              = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x9F1F,
					 .def = 0x8808},
	[AC97_AUX / 2]                = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x9F1F,
					 .def = 0x8808},
	[AC97_PCM / 2]                = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x9F1F,
					 .def = 0x8008},
	[AC97_REC_SEL / 2]            = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x707,
					 .def = 0x0},
	[AC97_REC_GAIN / 2]           = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .wmask = 0x8F0F,
					 .def = 0x8000},
	[AC97_GENERAL_PURPOSE / 2]    = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .def = 0x0,
					 .wmask = 0xA380},
	[AC97_3D_CONTROL / 2]         = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEREAD \
						| LM4550_REG_READONLY,
					 .def = 0x0101},
	[AC97_POWERDOWN / 2]          = {.flag = LM4550_REG_OK \
						| LM4550_REG_NOSHADOW \
						| LM4550_REG_NOSAVE,
					 .wmask = 0xFF00},
					/* may not write ones to
                                         * REF/ANL/DAC/ADC bits
                                         * FIXME: Is this ok?
                                         */
	[AC97_EXTENDED_ID / 2]        = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEREAD \
						| LM4550_REG_READONLY,
					 .def = 0x0201}, /* primary codec */
	[AC97_EXTENDED_STATUS / 2]    = {.flag = LM4550_REG_OK \
						| LM4550_REG_NOSHADOW \
						| LM4550_REG_NOSAVE,
					 .wmask = 0x1},
	[AC97_PCM_FRONT_DAC_RATE / 2] = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .def = 0xBB80,
					 .wmask = 0xFFFF},
	[AC97_PCM_LR_ADC_RATE / 2]    = {.flag = LM4550_REG_OK \
						| LM4550_REG_FAKEPROBE,
					 .def = 0xBB80,
					 .wmask = 0xFFFF},
	[AC97_VENDOR_ID1 / 2]         = {.flag = LM4550_REG_OK \
						| LM4550_REG_READONLY \
						| LM4550_REG_FAKEREAD,
					 .def = 0x4E53},
	[AC97_VENDOR_ID2 / 2]         = {.flag = LM4550_REG_OK \
						| LM4550_REG_READONLY \
						| LM4550_REG_FAKEREAD,
					 .def = 0x4350}
};


#define LM4550_RF_OK(reg)    (lm4550_regfile[reg / 2].flag & LM4550_REG_OK)


static void lm4550_regfile_init(void) { int i; for (i = 0; i < 64; i++) if (lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE) lm4550_regfile[i].value = lm4550_regfile[i].def; }

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static void lm4550_regfile_write_values_after_init(struct snd_ac97 *ac97) { int i; for (i = 0; i < 64; i++) if ((lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE) && (lm4550_regfile[i].value != lm4550_regfile[i].def)) { PDEBUG(CODEC_FAKE, "lm4550_regfile_write_values_after_" "init(): reg=0x%x value=0x%x / %d is different " "from def=0x%x / %d\n", i, lm4550_regfile[i].value, lm4550_regfile[i].value, lm4550_regfile[i].def, lm4550_regfile[i].def); snd_ac97_write(ac97, i * 2, lm4550_regfile[i].value); lm4550_regfile[i].flag |= LM4550_REG_DONEREAD; } }

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/* direct registers */ #define CR_REG(ml403_ac97cr, x) ((ml403_ac97cr)->port + CR_REG_##x) #define CR_REG_PLAYFIFO 0x00 #define CR_PLAYDATA(a) ((a) & 0xFFFF) #define CR_REG_RECFIFO 0x04 #define CR_RECDATA(a) ((a) & 0xFFFF) #define CR_REG_STATUS 0x08 #define CR_RECOVER (1<<7) #define CR_PLAYUNDER (1<<6) #define CR_CODECREADY (1<<5) #define CR_RAF (1<<4) #define CR_RECEMPTY (1<<3) #define CR_RECFULL (1<<2) #define CR_PLAYHALF (1<<1) #define CR_PLAYFULL (1<<0) #define CR_REG_RESETFIFO 0x0C #define CR_RECRESET (1<<1) #define CR_PLAYRESET (1<<0) #define CR_REG_CODEC_ADDR 0x10 /* UG082 says: * #define CR_CODEC_ADDR(a) ((a) << 1) * #define CR_CODEC_READ (1<<0) * #define CR_CODEC_WRITE (0<<0) */ /* RefDesign example says: */ #define CR_CODEC_ADDR(a) ((a) << 0) #define CR_CODEC_READ (1<<7) #define CR_CODEC_WRITE (0<<7) #define CR_REG_CODEC_DATAREAD 0x14 #define CR_CODEC_DATAREAD(v) ((v) & 0xFFFF) #define CR_REG_CODEC_DATAWRITE 0x18 #define CR_CODEC_DATAWRITE(v) ((v) & 0xFFFF) #define CR_FIFO_SIZE 32 struct snd_ml403_ac97cr { /* lock for access to (controller) registers */ spinlock_t reg_lock; /* mutex for the whole sequence of accesses to (controller) registers * which affect codec registers */ struct mutex cdc_mutex; int irq; /* for playback */ int enable_irq; /* for playback */ int capture_irq; int enable_capture_irq; struct resource *res_port; void *port; struct snd_ac97 *ac97; int ac97_fake; #ifdef CODEC_STAT int ac97_read; int ac97_write; #endif struct platform_device *pfdev; struct snd_card *card; struct snd_pcm *pcm; struct snd_pcm_substream *playback_substream; struct snd_pcm_substream *capture_substream; struct snd_pcm_indirect2 ind_rec; /* for playback */ struct snd_pcm_indirect2 capture_ind2_rec; }; static struct snd_pcm_hardware snd_ml403_ac97cr_playback = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_BE, .rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000), .rate_min = 4000, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = CR_FIFO_SIZE/2, .period_bytes_max = (64*1024), .periods_min = 2, .periods_max = (128*1024)/(CR_FIFO_SIZE/2), .fifo_size = 0, }; static struct snd_pcm_hardware snd_ml403_ac97cr_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID), .formats = SNDRV_PCM_FMTBIT_S16_BE, .rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000), .rate_min = 4000, .rate_max = 48000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = (128*1024), .period_bytes_min = CR_FIFO_SIZE/2, .period_bytes_max = (64*1024), .periods_min = 2, .periods_max = (128*1024)/(CR_FIFO_SIZE/2), .fifo_size = 0, };
static size_t snd_ml403_ac97cr_playback_ind2_zero(struct snd_pcm_substream *substream, struct snd_pcm_indirect2 *rec) { struct snd_ml403_ac97cr *ml403_ac97cr; int copied_words = 0; u32 full = 0; ml403_ac97cr = snd_pcm_substream_chip(substream); spin_lock(&ml403_ac97cr->reg_lock); while ((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_PLAYFULL)) != CR_PLAYFULL) { out_be32(CR_REG(ml403_ac97cr, PLAYFIFO), 0); copied_words++; } rec->hw_ready = 0; spin_unlock(&ml403_ac97cr->reg_lock); return (size_t) (copied_words * 2); }

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static size_t snd_ml403_ac97cr_playback_ind2_copy(struct snd_pcm_substream *substream, struct snd_pcm_indirect2 *rec, size_t bytes) { struct snd_ml403_ac97cr *ml403_ac97cr; u16 *src; int copied_words = 0; u32 full = 0; ml403_ac97cr = snd_pcm_substream_chip(substream); src = (u16 *)(substream->runtime->dma_area + rec->sw_data); spin_lock(&ml403_ac97cr->reg_lock); while (((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_PLAYFULL)) != CR_PLAYFULL) && (bytes > 1)) { out_be32(CR_REG(ml403_ac97cr, PLAYFIFO), CR_PLAYDATA(src[copied_words])); copied_words++; bytes = bytes - 2; } if (full != CR_PLAYFULL) rec->hw_ready = 1; else rec->hw_ready = 0; spin_unlock(&ml403_ac97cr->reg_lock); return (size_t) (copied_words * 2); }

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static size_t snd_ml403_ac97cr_capture_ind2_null(struct snd_pcm_substream *substream, struct snd_pcm_indirect2 *rec) { struct snd_ml403_ac97cr *ml403_ac97cr; int copied_words = 0; u32 empty = 0; ml403_ac97cr = snd_pcm_substream_chip(substream); spin_lock(&ml403_ac97cr->reg_lock); while ((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_RECEMPTY)) != CR_RECEMPTY) { volatile u32 trash; trash = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr, RECFIFO))); /* Hmmmm, really necessary? Don't want call to in_be32() * to be optimised away! */ trash++; copied_words++; } rec->hw_ready = 0; spin_unlock(&ml403_ac97cr->reg_lock); return (size_t) (copied_words * 2); }

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static size_t snd_ml403_ac97cr_capture_ind2_copy(struct snd_pcm_substream *substream, struct snd_pcm_indirect2 *rec, size_t bytes) { struct snd_ml403_ac97cr *ml403_ac97cr; u16 *dst; int copied_words = 0; u32 empty = 0; ml403_ac97cr = snd_pcm_substream_chip(substream); dst = (u16 *)(substream->runtime->dma_area + rec->sw_data); spin_lock(&ml403_ac97cr->reg_lock); while (((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_RECEMPTY)) != CR_RECEMPTY) && (bytes > 1)) { dst[copied_words] = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr, RECFIFO))); copied_words++; bytes = bytes - 2; } if (empty != CR_RECEMPTY) rec->hw_ready = 1; else rec->hw_ready = 0; spin_unlock(&ml403_ac97cr->reg_lock); return (size_t) (copied_words * 2); }

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static snd_pcm_uframes_t snd_ml403_ac97cr_pcm_pointer(struct snd_pcm_substream *substream) { struct snd_ml403_ac97cr *ml403_ac97cr; struct snd_pcm_indirect2 *ind2_rec = NULL; ml403_ac97cr = snd_pcm_substream_chip(substream); if (substream == ml403_ac97cr->playback_substream) ind2_rec = &ml403_ac97cr->ind_rec; if (substream == ml403_ac97cr->capture_substream) ind2_rec = &ml403_ac97cr->capture_ind2_rec; if (ind2_rec != NULL) return snd_pcm_indirect2_pointer(substream, ind2_rec); return (snd_pcm_uframes_t) 0; }

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static int snd_ml403_ac97cr_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_ml403_ac97cr *ml403_ac97cr; int err = 0; ml403_ac97cr = snd_pcm_substream_chip(substream); switch (cmd) { case SNDRV_PCM_TRIGGER_START: PDEBUG(WORK_INFO, "trigger(playback): START\n"); ml403_ac97cr->ind_rec.hw_ready = 1; /* clear play FIFO */ out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_PLAYRESET); /* enable play irq */ ml403_ac97cr->enable_irq = 1; enable_irq(ml403_ac97cr->irq); break; case SNDRV_PCM_TRIGGER_STOP: PDEBUG(WORK_INFO, "trigger(playback): STOP\n"); ml403_ac97cr->ind_rec.hw_ready = 0; #ifdef SND_PCM_INDIRECT2_STAT snd_pcm_indirect2_stat(substream, &ml403_ac97cr->ind_rec); #endif /* disable play irq */ disable_irq_nosync(ml403_ac97cr->irq); ml403_ac97cr->enable_irq = 0; break; default: err = -EINVAL; break; } PDEBUG(WORK_INFO, "trigger(playback): (done)\n"); return err; }

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static int snd_ml403_ac97cr_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_ml403_ac97cr *ml403_ac97cr; int err = 0; ml403_ac97cr = snd_pcm_substream_chip(substream); switch (cmd) { case SNDRV_PCM_TRIGGER_START: PDEBUG(WORK_INFO, "trigger(capture): START\n"); ml403_ac97cr->capture_ind2_rec.hw_ready = 0; /* clear record FIFO */ out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_RECRESET); /* enable record irq */ ml403_ac97cr->enable_capture_irq = 1; enable_irq(ml403_ac97cr->capture_irq); break; case SNDRV_PCM_TRIGGER_STOP: PDEBUG(WORK_INFO, "trigger(capture): STOP\n"); ml403_ac97cr->capture_ind2_rec.hw_ready = 0; #ifdef SND_PCM_INDIRECT2_STAT snd_pcm_indirect2_stat(substream, &ml403_ac97cr->capture_ind2_rec); #endif /* disable capture irq */ disable_irq_nosync(ml403_ac97cr->capture_irq); ml403_ac97cr->enable_capture_irq = 0; break; default: err = -EINVAL; break; } PDEBUG(WORK_INFO, "trigger(capture): (done)\n"); return err; }

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static int snd_ml403_ac97cr_pcm_playback_prepare(struct snd_pcm_substream *substream) { struct snd_ml403_ac97cr *ml403_ac97cr; struct snd_pcm_runtime *runtime; ml403_ac97cr = snd_pcm_substream_chip(substream); runtime = substream->runtime; PDEBUG(WORK_INFO, "prepare(): period_bytes=%d, minperiod_bytes=%d\n", snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2); /* set sampling rate */ snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate); PDEBUG(WORK_INFO, "prepare(): rate=%d\n", runtime->rate); /* init struct for intermediate buffer */ memset(&ml403_ac97cr->ind_rec, 0, sizeof(struct snd_pcm_indirect2)); ml403_ac97cr->ind_rec.hw_buffer_size = CR_FIFO_SIZE; ml403_ac97cr->ind_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); ml403_ac97cr->ind_rec.min_periods = -1; ml403_ac97cr->ind_rec.min_multiple = snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2); PDEBUG(WORK_INFO, "prepare(): hw_buffer_size=%d, " "sw_buffer_size=%d, min_multiple=%d\n", CR_FIFO_SIZE, ml403_ac97cr->ind_rec.sw_buffer_size, ml403_ac97cr->ind_rec.min_multiple); return 0; }

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static int snd_ml403_ac97cr_pcm_capture_prepare(struct snd_pcm_substream *substream) { struct snd_ml403_ac97cr *ml403_ac97cr; struct snd_pcm_runtime *runtime; ml403_ac97cr = snd_pcm_substream_chip(substream); runtime = substream->runtime; PDEBUG(WORK_INFO, "prepare(capture): period_bytes=%d, minperiod_bytes=%d\n", snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2); /* set sampling rate */ snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); PDEBUG(WORK_INFO, "prepare(capture): rate=%d\n", runtime->rate); /* init struct for intermediate buffer */ memset(&ml403_ac97cr->capture_ind2_rec, 0, sizeof(struct snd_pcm_indirect2)); ml403_ac97cr->capture_ind2_rec.hw_buffer_size = CR_FIFO_SIZE; ml403_ac97cr->capture_ind2_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); ml403_ac97cr->capture_ind2_rec.min_multiple = snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2); PDEBUG(