Release 4.9 arch/arm/kernel/smp_tlb.c

Directory: arch/arm/kernel
/*
 *  linux/arch/arm/kernel/smp_tlb.c
 *
 *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/preempt.h>
#include <linux/smp.h>

#include <asm/smp_plat.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>

/**********************************************************************/

/*
 * TLB operations
 */

struct tlb_args {
	
struct vm_area_struct *ta_vma;
	
unsigned long ta_start;
	
unsigned long ta_end;
};



static inline void ipi_flush_tlb_all(void *ignored)
{
	local_flush_tlb_all();
}

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russell king russell king 14 100.00% 1 100.00%
Total 14 100.00% 1 100.00%



static inline void ipi_flush_tlb_mm(void *arg)
{
	struct mm_struct *mm = (struct mm_struct *)arg;

	local_flush_tlb_mm(mm);
}

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russell king russell king 28 100.00% 1 100.00%
Total 28 100.00% 1 100.00%



static inline void ipi_flush_tlb_page(void *arg)
{
	struct tlb_args *ta = (struct tlb_args *)arg;

	local_flush_tlb_page(ta->ta_vma, ta->ta_start);
}

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russell king russell king 34 100.00% 1 100.00%
Total 34 100.00% 1 100.00%



static inline void ipi_flush_tlb_kernel_page(void *arg)
{
	struct tlb_args *ta = (struct tlb_args *)arg;

	local_flush_tlb_kernel_page(ta->ta_start);
}

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russell king russell king 30 100.00% 1 100.00%
Total 30 100.00% 1 100.00%



static inline void ipi_flush_tlb_range(void *arg)
{
	struct tlb_args *ta = (struct tlb_args *)arg;

	local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
}

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russell king russell king 38 100.00% 1 100.00%
Total 38 100.00% 1 100.00%



static inline void ipi_flush_tlb_kernel_range(void *arg)
{
	struct tlb_args *ta = (struct tlb_args *)arg;

	local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
}

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russell king russell king 34 100.00% 1 100.00%
Total 34 100.00% 1 100.00%



static inline void ipi_flush_bp_all(void *ignored)
{
	local_flush_bp_all();
}

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will deacon will deacon 14 100.00% 1 100.00%
Total 14 100.00% 1 100.00%

#ifdef CONFIG_ARM_ERRATA_798181

bool (*erratum_a15_798181_handler)(void);



static bool erratum_a15_798181_partial(void)
{
	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
	dsb(ish);
	return false;
}

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rob herring rob herring 17 100.00% 1 100.00%
Total 17 100.00% 1 100.00%



static bool erratum_a15_798181_broadcast(void)
{
	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
	dsb(ish);
	return true;
}

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rob herring rob herring 17 100.00% 1 100.00%
Total 17 100.00% 1 100.00%



void erratum_a15_798181_init(void)
{
	unsigned int midr = read_cpuid_id();
	unsigned int revidr = read_cpuid(CPUID_REVIDR);

	/* Brahma-B15 r0p0..r0p2 affected
         * Cortex-A15 r0p0..r3p3 w/o ECO fix affected
         * Fixes applied to A15 with respect to the revision and revidr are:
         *
         * r0p0-r2p1: No fixes applied
         * r2p2,r2p3:
         *      REVIDR[4]: 798181 Moving a virtual page that is being accessed
         *                 by an active process can lead to unexpected behavior
         *      REVIDR[9]: Not defined
         * r2p4,r3p0,r3p1,r3p2:
         *      REVIDR[4]: 798181 Moving a virtual page that is being accessed
         *                 by an active process can lead to unexpected behavior
         *      REVIDR[9]: 798181 Moving a virtual page that is being accessed
         *                 by an active process can lead to unexpected behavior
         *                 - This is an update to a previously released ECO.
         * r3p3:
         *      REVIDR[4]: Reserved
         *      REVIDR[9]: 798181 Moving a virtual page that is being accessed
         *                 by an active process can lead to unexpected behavior
         *                 - This is an update to a previously released ECO.
         *
         * Handling:
         *      REVIDR[9] set -> No WA
         *      REVIDR[4] set, REVIDR[9] cleared -> Partial WA
         *      Both cleared -> Full WA
         */
	if ((midr & 0xff0ffff0) == 0x420f00f0 && midr <= 0x420f00f2) {
		erratum_a15_798181_handler = erratum_a15_798181_broadcast;
	} else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x412fc0f2) {
		erratum_a15_798181_handler = erratum_a15_798181_broadcast;
	} else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x412fc0f4) {
		if (revidr & 0x10)
			erratum_a15_798181_handler =
				erratum_a15_798181_partial;
		else
			erratum_a15_798181_handler =
				erratum_a15_798181_broadcast;
	} else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x413fc0f3) {
		if ((revidr & 0x210) == 0)
			erratum_a15_798181_handler =
				erratum_a15_798181_broadcast;
		else if (revidr & 0x10)
			erratum_a15_798181_handler =
				erratum_a15_798181_partial;
	} else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x414fc0f0) {
		if ((revidr & 0x200) == 0)
			erratum_a15_798181_handler =
				erratum_a15_798181_partial;
	}
}
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matija glavinic pecotic matija glavinic pecotic 96 56.47% 1 33.33%
rob herring rob herring 52 30.59% 1 33.33%
gregory fong gregory fong 22 12.94% 1 33.33%
Total 170 100.00% 3 100.00%

#endif



static void ipi_flush_tlb_a15_erratum(void *arg)
{
	dmb();
}

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catalin marinas catalin marinas 13 100.00% 1 100.00%
Total 13 100.00% 1 100.00%



static void broadcast_tlb_a15_erratum(void)
{
	if (!erratum_a15_798181())
		return;

	smp_call_function(ipi_flush_tlb_a15_erratum, NULL, 1);
}

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catalin marinas catalin marinas 24 100.00% 2 100.00%
Total 24 100.00% 2 100.00%



static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
{
	int this_cpu;
	cpumask_t mask = { CPU_BITS_NONE };

	if (!erratum_a15_798181())
		return;

	this_cpu = get_cpu();
	a15_erratum_get_cpumask(this_cpu, mm, &mask);
	smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
	put_cpu();
}

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catalin marinas catalin marinas 56 96.55% 2 66.67%
marc zyngier marc zyngier 2 3.45% 1 33.33%
Total 58 100.00% 3 100.00%



void flush_tlb_all(void)
{
	if (tlb_ops_need_broadcast())
		on_each_cpu(ipi_flush_tlb_all, NULL, 1);
	else
		__flush_tlb_all();
	broadcast_tlb_a15_erratum();
}

Contributors
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russell king russell king 24 85.71% 1 33.33%
catalin marinas catalin marinas 3 10.71% 1 33.33%
will deacon will deacon 1 3.57% 1 33.33%
Total 28 100.00% 3 100.00%



void flush_tlb_mm(struct mm_struct *mm)
{
	if (tlb_ops_need_broadcast())
		on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
	else
		__flush_tlb_mm(mm);
	broadcast_tlb_mm_a15_erratum(mm);
}

Contributors
Person Tokens Prop Commits CommitProp
russell king russell king 29 72.50% 1 25.00%
catalin marinas catalin marinas 5 12.50% 1 25.00%
gilad ben-yossef gilad ben-yossef 5 12.50% 1 25.00%
will deacon will deacon 1 2.50% 1 25.00%
Total 40 100.00% 4 100.00%



void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
{
	if (tlb_ops_need_broadcast()) {
		struct tlb_args ta;
		ta.ta_vma = vma;
		ta.ta_start = uaddr;
		on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page,
					&ta, 1);
	} else
		__flush_tlb_page(vma, uaddr);
	broadcast_tlb_mm_a15_erratum(vma->vm_mm);
}

Contributors
Person Tokens Prop Commits CommitProp
russell king russell king 54 78.26% 1 25.00%
catalin marinas catalin marinas 7 10.14% 1 25.00%
gilad ben-yossef gilad ben-yossef 7 10.14% 1 25.00%
will deacon will deacon 1 1.45% 1 25.00%
Total 69 100.00% 4 100.00%



void flush_tlb_kernel_page(unsigned long kaddr)
{
	if (tlb_ops_need_broadcast()) {
		struct tlb_args ta;
		ta.ta_start = kaddr;
		on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
	} else
		__flush_tlb_kernel_page(kaddr);
	broadcast_tlb_a15_erratum();
}

Contributors
Person Tokens Prop Commits CommitProp
russell king russell king 41 91.11% 1 33.33%
catalin marinas catalin marinas 3 6.67% 1 33.33%
will deacon will deacon 1 2.22% 1 33.33%
Total 45 100.00% 3 100.00%



void flush_tlb_range(struct vm_area_struct *vma,
                     unsigned long start, unsigned long end)
{
	if (tlb_ops_need_broadcast()) {
		struct tlb_args ta;
		ta.ta_vma = vma;
		ta.ta_start = start;
		ta.ta_end = end;
		on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range,
					&ta, 1);
	} else
		local_flush_tlb_range(vma, start, end);
	broadcast_tlb_mm_a15_erratum(vma->vm_mm);
}

Contributors
Person Tokens Prop Commits CommitProp
russell king russell king 67 82.72% 1 33.33%
gilad ben-yossef gilad ben-yossef 7 8.64% 1 33.33%
catalin marinas catalin marinas 7 8.64% 1 33.33%
Total 81 100.00% 3 100.00%



void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	if (tlb_ops_need_broadcast()) {
		struct tlb_args ta;
		ta.ta_start = start;
		ta.ta_end = end;
		on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
	} else
		local_flush_tlb_kernel_range(start, end);
	broadcast_tlb_a15_erratum();
}

Contributors
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russell king russell king 54 94.74% 1 50.00%
catalin marinas catalin marinas 3 5.26% 1 50.00%
Total 57 100.00% 2 100.00%



void flush_bp_all(void)
{
	if (tlb_ops_need_broadcast())
		on_each_cpu(ipi_flush_bp_all, NULL, 1);
	else
		__flush_bp_all();
}
Contributors
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will deacon will deacon 25 100.00% 2 100.00%
Total 25 100.00% 2 100.00%

Overall Contributors
Person Tokens Prop Commits CommitProp
russell king russell king 480 54.18% 1 9.09%
catalin marinas catalin marinas 124 14.00% 2 18.18%
rob herring rob herring 100 11.29% 1 9.09%
matija glavinic pecotic matija glavinic pecotic 96 10.84% 1 9.09%
will deacon will deacon 43 4.85% 3 27.27%
gregory fong gregory fong 22 2.48% 1 9.09%
gilad ben-yossef gilad ben-yossef 19 2.14% 1 9.09%
marc zyngier marc zyngier 2 0.23% 1 9.09%
Total 886 100.00% 11 100.00%
  Directory: arch/arm/kernel
	Person	Tokens	Prop	Commits	CommitProp
russell king	russell king	14	100.00%	1	100.00%
	Total	14	100.00%	1	100.00%
cregit-Linux how code gets into the kernel

Release 4.9 arch/arm/kernel/smp_tlb.c

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