Release 4.9 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv31.h"
#include <subdev/instmem.h>
#include <nvif/class.h>
bool
nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
{
struct nvkm_instmem *imem = device->imem;
u32 inst = data << 4;
u32 dma0 = nvkm_instmem_rd32(imem, inst + 0);
u32 dma1 = nvkm_instmem_rd32(imem, inst + 4);
u32 dma2 = nvkm_instmem_rd32(imem, inst + 8);
u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
u32 size = dma1 + 1;
/* only allow linear DMA objects */
if (!(dma0 & 0x00002000))
return false;
if (mthd == 0x0190) {
/* DMA_CMD */
nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000));
nvkm_wr32(device, 0x00b334, base);
nvkm_wr32(device, 0x00b324, size);
} else
if (mthd == 0x01a0) {
/* DMA_DATA */
nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
nvkm_wr32(device, 0x00b360, base);
nvkm_wr32(device, 0x00b364, size);
} else {
/* DMA_IMAGE, VRAM only */
if (dma0 & 0x00030000)
return false;
nvkm_wr32(device, 0x00b370, base);
nvkm_wr32(device, 0x00b374, size);
}
return true;
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| ilia mirkin | ilia mirkin | 189 | 84.38% | 1 | 25.00% |
| ben skeggs | ben skeggs | 35 | 15.62% | 3 | 75.00% |
| Total | 224 | 100.00% | 4 | 100.00% |
static const struct nv31_mpeg_func
nv40_mpeg = {
.mthd_dma = nv40_mpeg_mthd_dma,
};
int
nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
{
return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg);
}
Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| ben skeggs | ben skeggs | 32 | 100.00% | 3 | 100.00% |
| Total | 32 | 100.00% | 3 | 100.00% |
Overall Contributors
| Person | Tokens | Prop | Commits | CommitProp |
| ilia mirkin | ilia mirkin | 189 | 67.74% | 1 | 11.11% |
| ben skeggs | ben skeggs | 90 | 32.26% | 8 | 88.89% |
| Total | 279 | 100.00% | 9 | 100.00% |