| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Alex Deucher | 7553 | 100.00% | 1 | 100.00% |
| Total | 7553 | 1 |
/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _mmhub_1_0_OFFSET_HEADER #define _mmhub_1_0_OFFSET_HEADER // addressBlock: mmhub_dagbdec // base address: 0x68000 #define mmDAGB0_RDCLI0 0x0000 #define mmDAGB0_RDCLI0_BASE_IDX 0 #define mmDAGB0_RDCLI1 0x0001 #define mmDAGB0_RDCLI1_BASE_IDX 0 #define mmDAGB0_RDCLI2 0x0002 #define mmDAGB0_RDCLI2_BASE_IDX 0 #define mmDAGB0_RDCLI3 0x0003 #define mmDAGB0_RDCLI3_BASE_IDX 0 #define mmDAGB0_RDCLI4 0x0004 #define mmDAGB0_RDCLI4_BASE_IDX 0 #define mmDAGB0_RDCLI5 0x0005 #define mmDAGB0_RDCLI5_BASE_IDX 0 #define mmDAGB0_RDCLI6 0x0006 #define mmDAGB0_RDCLI6_BASE_IDX 0 #define mmDAGB0_RDCLI7 0x0007 #define mmDAGB0_RDCLI7_BASE_IDX 0 #define mmDAGB0_RDCLI8 0x0008 #define mmDAGB0_RDCLI8_BASE_IDX 0 #define mmDAGB0_RDCLI9 0x0009 #define mmDAGB0_RDCLI9_BASE_IDX 0 #define mmDAGB0_RDCLI10 0x000a #define mmDAGB0_RDCLI10_BASE_IDX 0 #define mmDAGB0_RDCLI11 0x000b #define mmDAGB0_RDCLI11_BASE_IDX 0 #define mmDAGB0_RDCLI12 0x000c #define mmDAGB0_RDCLI12_BASE_IDX 0 #define mmDAGB0_RDCLI13 0x000d #define mmDAGB0_RDCLI13_BASE_IDX 0 #define mmDAGB0_RDCLI14 0x000e #define mmDAGB0_RDCLI14_BASE_IDX 0 #define mmDAGB0_RDCLI15 0x000f #define mmDAGB0_RDCLI15_BASE_IDX 0 #define mmDAGB0_RD_CNTL 0x0010 #define mmDAGB0_RD_CNTL_BASE_IDX 0 #define mmDAGB0_RD_GMI_CNTL 0x0011 #define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 #define mmDAGB0_RD_ADDR_DAGB 0x0012 #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 #define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015 #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 #define mmDAGB0_RD_VC0_CNTL 0x001c #define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 #define mmDAGB0_RD_VC1_CNTL 0x001d #define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 #define mmDAGB0_RD_VC2_CNTL 0x001e #define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 #define mmDAGB0_RD_VC3_CNTL 0x001f #define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 #define mmDAGB0_RD_VC4_CNTL 0x0020 #define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 #define mmDAGB0_RD_VC5_CNTL 0x0021 #define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 #define mmDAGB0_RD_VC6_CNTL 0x0022 #define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 #define mmDAGB0_RD_VC7_CNTL 0x0023 #define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 #define mmDAGB0_RD_CNTL_MISC 0x0024 #define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 #define mmDAGB0_RD_TLB_CREDIT 0x0025 #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 #define mmDAGB0_RDCLI_ASK_PENDING 0x0026 #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 #define mmDAGB0_RDCLI_GO_PENDING 0x0027 #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 #define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028 #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 #define mmDAGB0_RDCLI_TLB_PENDING 0x0029 #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 #define mmDAGB0_RDCLI_OARB_PENDING 0x002a #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 #define mmDAGB0_RDCLI_OSD_PENDING 0x002b #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI0 0x002c #define mmDAGB0_WRCLI0_BASE_IDX 0 #define mmDAGB0_WRCLI1 0x002d #define mmDAGB0_WRCLI1_BASE_IDX 0 #define mmDAGB0_WRCLI2 0x002e #define mmDAGB0_WRCLI2_BASE_IDX 0 #define mmDAGB0_WRCLI3 0x002f #define mmDAGB0_WRCLI3_BASE_IDX 0 #define mmDAGB0_WRCLI4 0x0030 #define mmDAGB0_WRCLI4_BASE_IDX 0 #define mmDAGB0_WRCLI5 0x0031 #define mmDAGB0_WRCLI5_BASE_IDX 0 #define mmDAGB0_WRCLI6 0x0032 #define mmDAGB0_WRCLI6_BASE_IDX 0 #define mmDAGB0_WRCLI7 0x0033 #define mmDAGB0_WRCLI7_BASE_IDX 0 #define mmDAGB0_WRCLI8 0x0034 #define mmDAGB0_WRCLI8_BASE_IDX 0 #define mmDAGB0_WRCLI9 0x0035 #define mmDAGB0_WRCLI9_BASE_IDX 0 #define mmDAGB0_WRCLI10 0x0036 #define mmDAGB0_WRCLI10_BASE_IDX 0 #define mmDAGB0_WRCLI11 0x0037 #define mmDAGB0_WRCLI11_BASE_IDX 0 #define mmDAGB0_WRCLI12 0x0038 #define mmDAGB0_WRCLI12_BASE_IDX 0 #define mmDAGB0_WRCLI13 0x0039 #define mmDAGB0_WRCLI13_BASE_IDX 0 #define mmDAGB0_WRCLI14 0x003a #define mmDAGB0_WRCLI14_BASE_IDX 0 #define mmDAGB0_WRCLI15 0x003b #define mmDAGB0_WRCLI15_BASE_IDX 0 #define mmDAGB0_WR_CNTL 0x003c #define mmDAGB0_WR_CNTL_BASE_IDX 0 #define mmDAGB0_WR_GMI_CNTL 0x003d #define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 #define mmDAGB0_WR_ADDR_DAGB 0x003e #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040 #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 #define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041 #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042 #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043 #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 #define mmDAGB0_WR_DATA_DAGB 0x0048 #define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 #define mmDAGB0_WR_VC0_CNTL 0x004d #define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 #define mmDAGB0_WR_VC1_CNTL 0x004e #define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 #define mmDAGB0_WR_VC2_CNTL 0x004f #define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 #define mmDAGB0_WR_VC3_CNTL 0x0050 #define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 #define mmDAGB0_WR_VC4_CNTL 0x0051 #define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 #define mmDAGB0_WR_VC5_CNTL 0x0052 #define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 #define mmDAGB0_WR_VC6_CNTL 0x0053 #define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 #define mmDAGB0_WR_VC7_CNTL 0x0054 #define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 #define mmDAGB0_WR_CNTL_MISC 0x0055 #define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 #define mmDAGB0_WR_TLB_CREDIT 0x0056 #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 #define mmDAGB0_WR_DATA_CREDIT 0x0057 #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 #define mmDAGB0_WR_MISC_CREDIT 0x0058 #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 #define mmDAGB0_WRCLI_ASK_PENDING 0x0059 #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI_GO_PENDING 0x005a #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005b #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI_TLB_PENDING 0x005c #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI_OARB_PENDING 0x005d #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI_OSD_PENDING 0x005e #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x005f #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 #define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0060 #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 #define mmDAGB0_DAGB_DLY 0x0061 #define mmDAGB0_DAGB_DLY_BASE_IDX 0 #define mmDAGB0_CNTL_MISC 0x0062 #define mmDAGB0_CNTL_MISC_BASE_IDX 0 #define mmDAGB0_CNTL_MISC2 0x0063 #define mmDAGB0_CNTL_MISC2_BASE_IDX 0 #define mmDAGB0_FIFO_EMPTY 0x0064 #define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 #define mmDAGB0_FIFO_FULL 0x0065 #define mmDAGB0_FIFO_FULL_BASE_IDX 0 #define mmDAGB0_WR_CREDITS_FULL 0x0066 #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 #define mmDAGB0_RD_CREDITS_FULL 0x0067 #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 #define mmDAGB0_PERFCOUNTER_LO 0x0068 #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 #define mmDAGB0_PERFCOUNTER_HI 0x0069 #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 #define mmDAGB0_PERFCOUNTER0_CFG 0x006a #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 #define mmDAGB0_PERFCOUNTER1_CFG 0x006b #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 #define mmDAGB0_PERFCOUNTER2_CFG 0x006c #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 #define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x006d #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 #define mmDAGB0_RESERVE0 0x006e #define mmDAGB0_RESERVE0_BASE_IDX 0 #define mmDAGB0_RESERVE1 0x006f #define mmDAGB0_RESERVE1_BASE_IDX 0 #define mmDAGB0_RESERVE2 0x0070 #define mmDAGB0_RESERVE2_BASE_IDX 0 #define mmDAGB0_RESERVE3 0x0071 #define mmDAGB0_RESERVE3_BASE_IDX 0 #define mmDAGB0_RESERVE4 0x0072 #define mmDAGB0_RESERVE4_BASE_IDX 0 #define mmDAGB0_RESERVE5 0x0073 #define mmDAGB0_RESERVE5_BASE_IDX 0 #define mmDAGB0_RESERVE6 0x0074 #define mmDAGB0_RESERVE6_BASE_IDX 0 #define mmDAGB0_RESERVE7 0x0075 #define mmDAGB0_RESERVE7_BASE_IDX 0 #define mmDAGB0_RESERVE8 0x0076 #define mmDAGB0_RESERVE8_BASE_IDX 0 #define mmDAGB0_RESERVE9 0x0077 #define mmDAGB0_RESERVE9_BASE_IDX 0 #define mmDAGB0_RESERVE10 0x0078 #define mmDAGB0_RESERVE10_BASE_IDX 0 #define mmDAGB0_RESERVE11 0x0079 #define mmDAGB0_RESERVE11_BASE_IDX 0 #define mmDAGB0_RESERVE12 0x007a #define mmDAGB0_RESERVE12_BASE_IDX 0 #define mmDAGB0_RESERVE13 0x007b #define mmDAGB0_RESERVE13_BASE_IDX 0 #define mmDAGB0_RESERVE14 0x007c #define mmDAGB0_RESERVE14_BASE_IDX 0 #define mmDAGB0_RESERVE15 0x007d #define mmDAGB0_RESERVE15_BASE_IDX 0 #define mmDAGB0_RESERVE16 0x007e #define mmDAGB0_RESERVE16_BASE_IDX 0 #define mmDAGB0_RESERVE17 0x007f #define mmDAGB0_RESERVE17_BASE_IDX 0 #define mmDAGB1_RDCLI0 0x0080 #define mmDAGB1_RDCLI0_BASE_IDX 0 #define mmDAGB1_RDCLI1 0x0081 #define mmDAGB1_RDCLI1_BASE_IDX 0 #define mmDAGB1_RDCLI2 0x0082 #define mmDAGB1_RDCLI2_BASE_IDX 0 #define mmDAGB1_RDCLI3 0x0083 #define mmDAGB1_RDCLI3_BASE_IDX 0 #define mmDAGB1_RDCLI4 0x0084 #define mmDAGB1_RDCLI4_BASE_IDX 0 #define mmDAGB1_RDCLI5 0x0085 #define mmDAGB1_RDCLI5_BASE_IDX 0 #define mmDAGB1_RDCLI6 0x0086 #define mmDAGB1_RDCLI6_BASE_IDX 0 #define mmDAGB1_RDCLI7 0x0087 #define mmDAGB1_RDCLI7_BASE_IDX 0 #define mmDAGB1_RDCLI8 0x0088 #define mmDAGB1_RDCLI8_BASE_IDX 0 #define mmDAGB1_RDCLI9 0x0089 #define mmDAGB1_RDCLI9_BASE_IDX 0 #define mmDAGB1_RDCLI10 0x008a #define mmDAGB1_RDCLI10_BASE_IDX 0 #define mmDAGB1_RDCLI11 0x008b #define mmDAGB1_RDCLI11_BASE_IDX 0 #define mmDAGB1_RDCLI12 0x008c #define mmDAGB1_RDCLI12_BASE_IDX 0 #define mmDAGB1_RDCLI13 0x008d #define mmDAGB1_RDCLI13_BASE_IDX 0 #define mmDAGB1_RDCLI14 0x008e #define mmDAGB1_RDCLI14_BASE_IDX 0 #define mmDAGB1_RDCLI15 0x008f #define mmDAGB1_RDCLI15_BASE_IDX 0 #define mmDAGB1_RD_CNTL 0x0090 #define mmDAGB1_RD_CNTL_BASE_IDX 0 #define mmDAGB1_RD_GMI_CNTL 0x0091 #define mmDAGB1_RD_GMI_CNTL_BASE_IDX 0 #define mmDAGB1_RD_ADDR_DAGB 0x0092 #define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 0 #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 #define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095 #define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 #define mmDAGB1_RD_VC0_CNTL 0x009c #define mmDAGB1_RD_VC0_CNTL_BASE_IDX 0 #define mmDAGB1_RD_VC1_CNTL 0x009d #define mmDAGB1_RD_VC1_CNTL_BASE_IDX 0 #define mmDAGB1_RD_VC2_CNTL 0x009e #define mmDAGB1_RD_VC2_CNTL_BASE_IDX 0 #define mmDAGB1_RD_VC3_CNTL 0x009f #define mmDAGB1_RD_VC3_CNTL_BASE_IDX 0 #define mmDAGB1_RD_VC4_CNTL 0x00a0 #define mmDAGB1_RD_VC4_CNTL_BASE_IDX 0 #define mmDAGB1_RD_VC5_CNTL 0x00a1 #define mmDAGB1_RD_VC5_CNTL_BASE_IDX 0 #define mmDAGB1_RD_VC6_CNTL 0x00a2 #define mmDAGB1_RD_VC6_CNTL_BASE_IDX 0 #define mmDAGB1_RD_VC7_CNTL 0x00a3 #define mmDAGB1_RD_VC7_CNTL_BASE_IDX 0 #define mmDAGB1_RD_CNTL_MISC 0x00a4 #define mmDAGB1_RD_CNTL_MISC_BASE_IDX 0 #define mmDAGB1_RD_TLB_CREDIT 0x00a5 #define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 0 #define mmDAGB1_RDCLI_ASK_PENDING 0x00a6 #define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 #define mmDAGB1_RDCLI_GO_PENDING 0x00a7 #define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 #define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8 #define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 #define mmDAGB1_RDCLI_TLB_PENDING 0x00a9 #define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 #define mmDAGB1_RDCLI_OARB_PENDING 0x00aa #define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 #define mmDAGB1_RDCLI_OSD_PENDING 0x00ab #define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI0 0x00ac #define mmDAGB1_WRCLI0_BASE_IDX 0 #define mmDAGB1_WRCLI1 0x00ad #define mmDAGB1_WRCLI1_BASE_IDX 0 #define mmDAGB1_WRCLI2 0x00ae #define mmDAGB1_WRCLI2_BASE_IDX 0 #define mmDAGB1_WRCLI3 0x00af #define mmDAGB1_WRCLI3_BASE_IDX 0 #define mmDAGB1_WRCLI4 0x00b0 #define mmDAGB1_WRCLI4_BASE_IDX 0 #define mmDAGB1_WRCLI5 0x00b1 #define mmDAGB1_WRCLI5_BASE_IDX 0 #define mmDAGB1_WRCLI6 0x00b2 #define mmDAGB1_WRCLI6_BASE_IDX 0 #define mmDAGB1_WRCLI7 0x00b3 #define mmDAGB1_WRCLI7_BASE_IDX 0 #define mmDAGB1_WRCLI8 0x00b4 #define mmDAGB1_WRCLI8_BASE_IDX 0 #define mmDAGB1_WRCLI9 0x00b5 #define mmDAGB1_WRCLI9_BASE_IDX 0 #define mmDAGB1_WRCLI10 0x00b6 #define mmDAGB1_WRCLI10_BASE_IDX 0 #define mmDAGB1_WRCLI11 0x00b7 #define mmDAGB1_WRCLI11_BASE_IDX 0 #define mmDAGB1_WRCLI12 0x00b8 #define mmDAGB1_WRCLI12_BASE_IDX 0 #define mmDAGB1_WRCLI13 0x00b9 #define mmDAGB1_WRCLI13_BASE_IDX 0 #define mmDAGB1_WRCLI14 0x00ba #define mmDAGB1_WRCLI14_BASE_IDX 0 #define mmDAGB1_WRCLI15 0x00bb #define mmDAGB1_WRCLI15_BASE_IDX 0 #define mmDAGB1_WR_CNTL 0x00bc #define mmDAGB1_WR_CNTL_BASE_IDX 0 #define mmDAGB1_WR_GMI_CNTL 0x00bd #define mmDAGB1_WR_GMI_CNTL_BASE_IDX 0 #define mmDAGB1_WR_ADDR_DAGB 0x00be #define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 0 #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0 #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 #define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1 #define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2 #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3 #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 #define mmDAGB1_WR_DATA_DAGB 0x00c8 #define mmDAGB1_WR_DATA_DAGB_BASE_IDX 0 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 #define mmDAGB1_WR_VC0_CNTL 0x00cd #define mmDAGB1_WR_VC0_CNTL_BASE_IDX 0 #define mmDAGB1_WR_VC1_CNTL 0x00ce #define mmDAGB1_WR_VC1_CNTL_BASE_IDX 0 #define mmDAGB1_WR_VC2_CNTL 0x00cf #define mmDAGB1_WR_VC2_CNTL_BASE_IDX 0 #define mmDAGB1_WR_VC3_CNTL 0x00d0 #define mmDAGB1_WR_VC3_CNTL_BASE_IDX 0 #define mmDAGB1_WR_VC4_CNTL 0x00d1 #define mmDAGB1_WR_VC4_CNTL_BASE_IDX 0 #define mmDAGB1_WR_VC5_CNTL 0x00d2 #define mmDAGB1_WR_VC5_CNTL_BASE_IDX 0 #define mmDAGB1_WR_VC6_CNTL 0x00d3 #define mmDAGB1_WR_VC6_CNTL_BASE_IDX 0 #define mmDAGB1_WR_VC7_CNTL 0x00d4 #define mmDAGB1_WR_VC7_CNTL_BASE_IDX 0 #define mmDAGB1_WR_CNTL_MISC 0x00d5 #define mmDAGB1_WR_CNTL_MISC_BASE_IDX 0 #define mmDAGB1_WR_TLB_CREDIT 0x00d6 #define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 0 #define mmDAGB1_WR_DATA_CREDIT 0x00d7 #define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 0 #define mmDAGB1_WR_MISC_CREDIT 0x00d8 #define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 0 #define mmDAGB1_WRCLI_ASK_PENDING 0x00d9 #define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI_GO_PENDING 0x00da #define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00db #define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI_TLB_PENDING 0x00dc #define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI_OARB_PENDING 0x00dd #define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI_OSD_PENDING 0x00de #define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00df #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 #define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e0 #define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 #define mmDAGB1_DAGB_DLY 0x00e1 #define mmDAGB1_DAGB_DLY_BASE_IDX 0 #define mmDAGB1_CNTL_MISC 0x00e2 #define mmDAGB1_CNTL_MISC_BASE_IDX 0 #define mmDAGB1_CNTL_MISC2 0x00e3 #define mmDAGB1_CNTL_MISC2_BASE_IDX 0 #define mmDAGB1_FIFO_EMPTY 0x00e4 #define mmDAGB1_FIFO_EMPTY_BASE_IDX 0 #define mmDAGB1_FIFO_FULL 0x00e5 #define mmDAGB1_FIFO_FULL_BASE_IDX 0 #define mmDAGB1_WR_CREDITS_FULL 0x00e6 #define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 0 #define mmDAGB1_RD_CREDITS_FULL 0x00e7 #define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 0 #define mmDAGB1_PERFCOUNTER_LO 0x00e8 #define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 0 #define mmDAGB1_PERFCOUNTER_HI 0x00e9 #define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 0 #define mmDAGB1_PERFCOUNTER0_CFG 0x00ea #define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 #define mmDAGB1_PERFCOUNTER1_CFG 0x00eb #define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 #define mmDAGB1_PERFCOUNTER2_CFG 0x00ec #define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 #define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00ed #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 #define mmDAGB1_RESERVE0 0x00ee #define mmDAGB1_RESERVE0_BASE_IDX 0 #define mmDAGB1_RESERVE1 0x00ef #define mmDAGB1_RESERVE1_BASE_IDX 0 #define mmDAGB1_RESERVE2 0x00f0 #define mmDAGB1_RESERVE2_BASE_IDX 0 #define mmDAGB1_RESERVE3 0x00f1 #define mmDAGB1_RESERVE3_BASE_IDX 0 #define mmDAGB1_RESERVE4 0x00f2 #define mmDAGB1_RESERVE4_BASE_IDX 0 #define mmDAGB1_RESERVE5 0x00f3 #define mmDAGB1_RESERVE5_BASE_IDX 0 #define mmDAGB1_RESERVE6 0x00f4 #define mmDAGB1_RESERVE6_BASE_IDX 0 #define mmDAGB1_RESERVE7 0x00f5 #define mmDAGB1_RESERVE7_BASE_IDX 0 #define mmDAGB1_RESERVE8 0x00f6 #define mmDAGB1_RESERVE8_BASE_IDX 0 #define mmDAGB1_RESERVE9 0x00f7 #define mmDAGB1_RESERVE9_BASE_IDX 0 #define mmDAGB1_RESERVE10 0x00f8 #define mmDAGB1_RESERVE10_BASE_IDX 0 #define mmDAGB1_RESERVE11 0x00f9 #define mmDAGB1_RESERVE11_BASE_IDX 0 #define mmDAGB1_RESERVE12 0x00fa #define mmDAGB1_RESERVE12_BASE_IDX 0 #define mmDAGB1_RESERVE13 0x00fb #define mmDAGB1_RESERVE13_BASE_IDX 0 #define mmDAGB1_RESERVE14 0x00fc #define mmDAGB1_RESERVE14_BASE_IDX 0 #define mmDAGB1_RESERVE15 0x00fd #define mmDAGB1_RESERVE15_BASE_IDX 0 #define mmDAGB1_RESERVE16 0x00fe #define mmDAGB1_RESERVE16_BASE_IDX 0 #define mmDAGB1_RESERVE17 0x00ff #define mmDAGB1_RESERVE17_BASE_IDX 0 // addressBlock: mmhub_ea_mmeadec // base address: 0x68400 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 #define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 #define mmMMEA0_DRAM_RD_LAZY 0x0106 #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 #define mmMMEA0_DRAM_WR_LAZY 0x0107 #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 #define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 #define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 #define mmMMEA0_DRAM_PAGE_BURST 0x010a #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 #define mmMMEA0_DRAM_RD_PRI_AGE 0x010b #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 #define mmMMEA0_DRAM_WR_PRI_AGE 0x010c #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 #define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 #define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 #define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 #define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 #define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 #define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0132 #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0133 #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 #define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0134 #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0135 #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0136 #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 #define mmMMEA0_ADDRNORM_HOLE_CNTL 0x0141 #define mmMMEA0_ADDRNORM_HOLE_CNTL_BASE_IDX 0 #define mmMMEA0_ADDRDEC_BANK_CFG 0x0142 #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 #define mmMMEA0_ADDRDEC_MISC_CFG 0x0143 #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0144 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x0145 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x0146 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x0147 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x0148 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x0149 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014a #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x014b #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x014c #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x014d #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0158 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0159 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x015a #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x015b #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x015c #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x015d #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x015e #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x015f #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0160 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0161 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0162 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0163 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0164 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0165 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0166 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0167 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0168 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0169 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x016a #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x016b #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x016c #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x016d #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x016e #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x016f #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0170 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0171 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0172 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0173 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0174 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0175 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0176 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0177 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0178 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0179 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x017a #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x017b #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x017c #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x017d #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x017e #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x017f #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0180 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0181 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0182 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0183 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0184 #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0185 #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0186 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0187 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 #define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01d0 #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01d1 #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01d2 #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01d3 #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01d4 #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 #define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01d5 #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 #define mmMMEA0_IO_GROUP_BURST 0x01d6 #define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_AGE 0x01d7 #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_AGE 0x01d8 #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_QUEUING 0x01d9 #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_QUEUING 0x01da #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_FIXED 0x01db #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_FIXED 0x01dc #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_URGENCY 0x01dd #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_URGENCY 0x01de #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_URGENCY_MASK 0x01df #define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_URGENCY_MASK 0x01e0 #define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01e1 #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01e2 #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01e3 #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01e4 #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01e5 #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01e6 #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA0_SDP_ARB_DRAM 0x01e7 #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 #define mmMMEA0_SDP_ARB_FINAL 0x01e9 #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 #define mmMMEA0_SDP_DRAM_PRIORITY 0x01ea #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 #define mmMMEA0_SDP_IO_PRIORITY 0x01ec #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 #define mmMMEA0_SDP_CREDITS 0x01ed #define mmMMEA0_SDP_CREDITS_BASE_IDX 0 #define mmMMEA0_SDP_TAG_RESERVE0 0x01ee #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 #define mmMMEA0_SDP_TAG_RESERVE1 0x01ef #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 #define mmMMEA0_SDP_VCC_RESERVE0 0x01f0 #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 #define mmMMEA0_SDP_VCC_RESERVE1 0x01f1 #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 #define mmMMEA0_SDP_VCD_RESERVE0 0x01f2 #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 #define mmMMEA0_SDP_VCD_RESERVE1 0x01f3 #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 #define mmMMEA0_SDP_REQ_CNTL 0x01f4 #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 #define mmMMEA0_MISC 0x01f5 #define mmMMEA0_MISC_BASE_IDX 0 #define mmMMEA0_LATENCY_SAMPLING 0x01f6 #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 #define mmMMEA0_PERFCOUNTER_LO 0x01f7 #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 #define mmMMEA0_PERFCOUNTER_HI 0x01f8 #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 #define mmMMEA0_PERFCOUNTER0_CFG 0x01f9 #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 #define mmMMEA0_PERFCOUNTER1_CFG 0x01fa #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 #define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x01fb #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 #define mmMMEA0_EDC_CNT 0x0201 #define mmMMEA0_EDC_CNT_BASE_IDX 0 #define mmMMEA0_EDC_CNT2 0x0202 #define mmMMEA0_EDC_CNT2_BASE_IDX 0 #define mmMMEA0_DSM_CNTL 0x0203 #define mmMMEA0_DSM_CNTL_BASE_IDX 0 #define mmMMEA0_DSM_CNTLA 0x0204 #define mmMMEA0_DSM_CNTLA_BASE_IDX 0 #define mmMMEA0_DSM_CNTLB 0x0205 #define mmMMEA0_DSM_CNTLB_BASE_IDX 0 #define mmMMEA0_DSM_CNTL2 0x0206 #define mmMMEA0_DSM_CNTL2_BASE_IDX 0 #define mmMMEA0_DSM_CNTL2A 0x0207 #define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 #define mmMMEA0_DSM_CNTL2B 0x0208 #define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 #define mmMMEA0_CGTT_CLK_CTRL 0x020a #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 #define mmMMEA0_EDC_MODE 0x020b #define mmMMEA0_EDC_MODE_BASE_IDX 0 #define mmMMEA0_ERR_STATUS 0x020c #define mmMMEA0_ERR_STATUS_BASE_IDX 0 #define mmMMEA0_MISC2 0x020d #define mmMMEA0_MISC2_BASE_IDX 0 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0240 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0241 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0242 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0243 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x0244 #define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 #define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x0245 #define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 #define mmMMEA1_DRAM_RD_LAZY 0x0246 #define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 0 #define mmMMEA1_DRAM_WR_LAZY 0x0247 #define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 0 #define mmMMEA1_DRAM_RD_CAM_CNTL 0x0248 #define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 #define mmMMEA1_DRAM_WR_CAM_CNTL 0x0249 #define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 #define mmMMEA1_DRAM_PAGE_BURST 0x024a #define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 #define mmMMEA1_DRAM_RD_PRI_AGE 0x024b #define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 #define mmMMEA1_DRAM_WR_PRI_AGE 0x024c #define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 #define mmMMEA1_DRAM_RD_PRI_QUEUING 0x024d #define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 #define mmMMEA1_DRAM_WR_PRI_QUEUING 0x024e #define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 #define mmMMEA1_DRAM_RD_PRI_FIXED 0x024f #define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 #define mmMMEA1_DRAM_WR_PRI_FIXED 0x0250 #define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 #define mmMMEA1_DRAM_RD_PRI_URGENCY 0x0251 #define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 #define mmMMEA1_DRAM_WR_PRI_URGENCY 0x0252 #define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0253 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0254 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0255 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0256 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0257 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0258 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA1_ADDRNORM_BASE_ADDR0 0x0272 #define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0 #define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x0273 #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 #define mmMMEA1_ADDRNORM_BASE_ADDR1 0x0274 #define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0 #define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x0275 #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 #define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x0276 #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 #define mmMMEA1_ADDRNORM_HOLE_CNTL 0x0281 #define mmMMEA1_ADDRNORM_HOLE_CNTL_BASE_IDX 0 #define mmMMEA1_ADDRDEC_BANK_CFG 0x0282 #define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0 #define mmMMEA1_ADDRDEC_MISC_CFG 0x0283 #define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0284 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x0285 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x0286 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x0287 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x0288 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x0289 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x028a #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x028b #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x028c #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x028d #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x0298 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0299 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x029a #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x029b #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x029c #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x029d #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x029e #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x029f #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x02a0 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x02a1 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x02a2 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x02a3 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x02a4 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x02a5 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x02a6 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x02a7 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x02a8 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x02a9 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x02aa #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x02ab #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x02ac #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x02ad #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x02ae #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x02af #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x02b0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x02b1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x02b2 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x02b3 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x02b4 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x02b5 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x02b6 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x02b7 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x02b8 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x02b9 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x02ba #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x02bb #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x02bc #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x02bd #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x02be #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x02bf #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x02c0 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x02c1 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x02c2 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x02c3 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x02c4 #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x02c5 #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x02c6 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x02c7 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 #define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0310 #define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0311 #define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0312 #define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 #define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0313 #define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 #define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0314 #define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 #define mmMMEA1_IO_WR_COMBINE_FLUSH 0x0315 #define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 #define mmMMEA1_IO_GROUP_BURST 0x0316 #define mmMMEA1_IO_GROUP_BURST_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_AGE 0x0317 #define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_AGE 0x0318 #define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_QUEUING 0x0319 #define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_QUEUING 0x031a #define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_FIXED 0x031b #define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_FIXED 0x031c #define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_URGENCY 0x031d #define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_URGENCY 0x031e #define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_URGENCY_MASK 0x031f #define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_URGENCY_MASK 0x0320 #define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x0321 #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x0322 #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x0323 #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x0324 #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x0325 #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 #define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x0326 #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 #define mmMMEA1_SDP_ARB_DRAM 0x0327 #define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 0 #define mmMMEA1_SDP_ARB_FINAL 0x0329 #define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 0 #define mmMMEA1_SDP_DRAM_PRIORITY 0x032a #define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 #define mmMMEA1_SDP_IO_PRIORITY 0x032c #define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 #define mmMMEA1_SDP_CREDITS 0x032d #define mmMMEA1_SDP_CREDITS_BASE_IDX 0 #define mmMMEA1_SDP_TAG_RESERVE0 0x032e #define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 #define mmMMEA1_SDP_TAG_RESERVE1 0x032f #define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 #define mmMMEA1_SDP_VCC_RESERVE0 0x0330 #define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 #define mmMMEA1_SDP_VCC_RESERVE1 0x0331 #define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 #define mmMMEA1_SDP_VCD_RESERVE0 0x0332 #define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 #define mmMMEA1_SDP_VCD_RESERVE1 0x0333 #define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 #define mmMMEA1_SDP_REQ_CNTL 0x0334 #define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 0 #define mmMMEA1_MISC 0x0335 #define mmMMEA1_MISC_BASE_IDX 0 #define mmMMEA1_LATENCY_SAMPLING 0x0336 #define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 0 #define mmMMEA1_PERFCOUNTER_LO 0x0337 #define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 0 #define mmMMEA1_PERFCOUNTER_HI 0x0338 #define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 0 #define mmMMEA1_PERFCOUNTER0_CFG 0x0339 #define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 #define mmMMEA1_PERFCOUNTER1_CFG 0x033a #define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 #define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x033b #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 #define mmMMEA1_EDC_CNT 0x0341 #define mmMMEA1_EDC_CNT_BASE_IDX 0 #define mmMMEA1_EDC_CNT2 0x0342 #define mmMMEA1_EDC_CNT2_BASE_IDX 0 #define mmMMEA1_DSM_CNTL 0x0343 #define mmMMEA1_DSM_CNTL_BASE_IDX 0 #define mmMMEA1_DSM_CNTLA 0x0344 #define mmMMEA1_DSM_CNTLA_BASE_IDX 0 #define mmMMEA1_DSM_CNTLB 0x0345 #define mmMMEA1_DSM_CNTLB_BASE_IDX 0 #define mmMMEA1_DSM_CNTL2 0x0346 #define mmMMEA1_DSM_CNTL2_BASE_IDX 0 #define mmMMEA1_DSM_CNTL2A 0x0347 #define mmMMEA1_DSM_CNTL2A_BASE_IDX 0 #define mmMMEA1_DSM_CNTL2B 0x0348 #define mmMMEA1_DSM_CNTL2B_BASE_IDX 0 #define mmMMEA1_CGTT_CLK_CTRL 0x034a #define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 #define mmMMEA1_EDC_MODE 0x034b #define mmMMEA1_EDC_MODE_BASE_IDX 0 #define mmMMEA1_ERR_STATUS 0x034c #define mmMMEA1_ERR_STATUS_BASE_IDX 0 #define mmMMEA1_MISC2 0x034d #define mmMMEA1_MISC2_BASE_IDX 0 // addressBlock: mmhub_pctldec // base address: 0x68e00 #define mmPCTL_MISC 0x0380 #define mmPCTL_MISC_BASE_IDX 0 #define mmPCTL_MMHUB_DEEPSLEEP 0x0381 #define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 #define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 #define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 #define mmPCTL_PG_DAGB 0x0384 #define mmPCTL_PG_DAGB_BASE_IDX 0 #define mmPCTL0_RENG_RAM_INDEX 0x0385 #define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 #define mmPCTL0_RENG_RAM_DATA 0x0386 #define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 #define mmPCTL0_RENG_EXECUTE 0x0387 #define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 #define mmPCTL0_MISC 0x0388 #define mmPCTL0_MISC_BASE_IDX 0 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x0389 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038a #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x038b #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x038c #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x038d #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 #define mmPCTL1_RENG_RAM_INDEX 0x038e #define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 #define mmPCTL1_RENG_RAM_DATA 0x038f #define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 #define mmPCTL1_RENG_EXECUTE 0x0390 #define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 #define mmPCTL1_MISC 0x0391 #define mmPCTL1_MISC_BASE_IDX 0 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0392 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0393 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0394 #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x0395 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0396 #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 #define mmPCTL2_RENG_RAM_INDEX 0x0397 #define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 #define mmPCTL2_RENG_RAM_DATA 0x0398 #define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 #define mmPCTL2_RENG_EXECUTE 0x0399 #define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 #define mmPCTL2_MISC 0x039a #define mmPCTL2_MISC_BASE_IDX 0 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x039e #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039f #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 // addressBlock: mmhub_l1tlb_vml1dec // base address: 0x69600 #define mmMC_VM_MX_L1_TLB0_STATUS 0x0588 #define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB1_STATUS 0x0589 #define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB2_STATUS 0x058a #define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB3_STATUS 0x058b #define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB4_STATUS 0x058c #define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB5_STATUS 0x058d #define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB6_STATUS 0x058e #define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB7_STATUS 0x058f #define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 // addressBlock: mmhub_l1tlb_vml1pldec // base address: 0x69650 #define mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 #define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 #define mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 #define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 #define mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 #define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 #define mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 #define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 #define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 #define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 // addressBlock: mmhub_l1tlb_vml1prdec // base address: 0x69670 #define mmMC_VM_MX_L1_PERFCOUNTER_LO 0x059c #define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 #define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d #define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 // addressBlock: mmhub_utcl2_atcl2dec // base address: 0x69900 #define mmATC_L2_CNTL 0x0640 #define mmATC_L2_CNTL_BASE_IDX 0 #define mmATC_L2_CNTL2 0x0641 #define mmATC_L2_CNTL2_BASE_IDX 0 #define mmATC_L2_CACHE_DATA0 0x0644 #define mmATC_L2_CACHE_DATA0_BASE_IDX 0 #define mmATC_L2_CACHE_DATA1 0x0645 #define mmATC_L2_CACHE_DATA1_BASE_IDX 0 #define mmATC_L2_CACHE_DATA2 0x0646 #define mmATC_L2_CACHE_DATA2_BASE_IDX 0 #define mmATC_L2_CNTL3 0x0647 #define mmATC_L2_CNTL3_BASE_IDX 0 #define mmATC_L2_STATUS 0x0648 #define mmATC_L2_STATUS_BASE_IDX 0 #define mmATC_L2_STATUS2 0x0649 #define mmATC_L2_STATUS2_BASE_IDX 0 #define mmATC_L2_MISC_CG 0x064a #define mmATC_L2_MISC_CG_BASE_IDX 0 #define mmATC_L2_MEM_POWER_LS 0x064b #define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 #define mmATC_L2_CGTT_CLK_CTRL 0x064c #define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 // addressBlock: mmhub_utcl2_vml2pfdec // base address: 0x69a00 #define mmVM_L2_CNTL 0x0680 #define mmVM_L2_CNTL_BASE_IDX 0 #define mmVM_L2_CNTL2 0x0681 #define mmVM_L2_CNTL2_BASE_IDX 0 #define mmVM_L2_CNTL3 0x0682 #define mmVM_L2_CNTL3_BASE_IDX 0 #define mmVM_L2_STATUS 0x0683 #define mmVM_L2_STATUS_BASE_IDX 0 #define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0684 #define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 #define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 #define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 #define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 #define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_CNTL 0x0687 #define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0688 #define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0689 #define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068a #define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_STATUS 0x068b #define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068c #define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068d #define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068e #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x068f #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0691 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0692 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0693 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0694 #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0695 #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0696 #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 #define mmVM_L2_CNTL4 0x0697 #define mmVM_L2_CNTL4_BASE_IDX 0 #define mmVM_L2_MM_GROUP_RT_CLASSES 0x0698 #define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 #define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0699 #define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 #define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x069a #define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 #define mmVM_L2_CACHE_PARITY_CNTL 0x069b #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 #define mmVM_L2_CGTT_CLK_CTRL 0x069e #define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 // addressBlock: mmhub_utcl2_vml2vcdec // base address: 0x69b00 #define mmVM_CONTEXT0_CNTL 0x06c0 #define mmVM_CONTEXT0_CNTL_BASE_IDX 0 #define mmVM_CONTEXT1_CNTL 0x06c1 #define mmVM_CONTEXT1_CNTL_BASE_IDX 0 #define mmVM_CONTEXT2_CNTL 0x06c2 #define mmVM_CONTEXT2_CNTL_BASE_IDX 0 #define mmVM_CONTEXT3_CNTL 0x06c3 #define mmVM_CONTEXT3_CNTL_BASE_IDX 0 #define mmVM_CONTEXT4_CNTL 0x06c4 #define mmVM_CONTEXT4_CNTL_BASE_IDX 0 #define mmVM_CONTEXT5_CNTL 0x06c5 #define mmVM_CONTEXT5_CNTL_BASE_IDX 0 #define mmVM_CONTEXT6_CNTL 0x06c6 #define mmVM_CONTEXT6_CNTL_BASE_IDX 0 #define mmVM_CONTEXT7_CNTL 0x06c7 #define mmVM_CONTEXT7_CNTL_BASE_IDX 0 #define mmVM_CONTEXT8_CNTL 0x06c8 #define mmVM_CONTEXT8_CNTL_BASE_IDX 0 #define mmVM_CONTEXT9_CNTL 0x06c9 #define mmVM_CONTEXT9_CNTL_BASE_IDX 0 #define mmVM_CONTEXT10_CNTL 0x06ca #define mmVM_CONTEXT10_CNTL_BASE_IDX 0 #define mmVM_CONTEXT11_CNTL 0x06cb #define mmVM_CONTEXT11_CNTL_BASE_IDX 0 #define mmVM_CONTEXT12_CNTL 0x06cc #define mmVM_CONTEXT12_CNTL_BASE_IDX 0 #define mmVM_CONTEXT13_CNTL 0x06cd #define mmVM_CONTEXT13_CNTL_BASE_IDX 0 #define mmVM_CONTEXT14_CNTL 0x06ce #define mmVM_CONTEXT14_CNTL_BASE_IDX 0 #define mmVM_CONTEXT15_CNTL 0x06cf #define mmVM_CONTEXT15_CNTL_BASE_IDX 0 #define mmVM_CONTEXTS_DISABLE 0x06d0 #define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 #define mmVM_INVALIDATE_ENG0_SEM 0x06d1 #define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG1_SEM 0x06d2 #define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG2_SEM 0x06d3 #define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG3_SEM 0x06d4 #define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG4_SEM 0x06d5 #define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG5_SEM 0x06d6 #define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG6_SEM 0x06d7 #define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG7_SEM 0x06d8 #define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG8_SEM 0x06d9 #define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG9_SEM 0x06da #define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG10_SEM 0x06db #define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG11_SEM 0x06dc #define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG12_SEM 0x06dd #define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG13_SEM 0x06de #define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG14_SEM 0x06df #define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG15_SEM 0x06e0 #define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG16_SEM 0x06e1 #define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG17_SEM 0x06e2 #define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 #define mmVM_INVALIDATE_ENG0_REQ 0x06e3 #define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG1_REQ 0x06e4 #define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG2_REQ 0x06e5 #define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG3_REQ 0x06e6 #define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG4_REQ 0x06e7 #define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG5_REQ 0x06e8 #define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG6_REQ 0x06e9 #define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG7_REQ 0x06ea #define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG8_REQ 0x06eb #define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG9_REQ 0x06ec #define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG10_REQ 0x06ed #define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG11_REQ 0x06ee #define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG12_REQ 0x06ef #define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG13_REQ 0x06f0 #define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG14_REQ 0x06f1 #define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG15_REQ 0x06f2 #define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG16_REQ 0x06f3 #define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG17_REQ 0x06f4 #define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 #define mmVM_INVALIDATE_ENG0_ACK 0x06f5 #define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG1_ACK 0x06f6 #define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG2_ACK 0x06f7 #define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG3_ACK 0x06f8 #define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG4_ACK 0x06f9 #define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG5_ACK 0x06fa #define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG6_ACK 0x06fb #define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG7_ACK 0x06fc #define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG8_ACK 0x06fd #define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG9_ACK 0x06fe #define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG10_ACK 0x06ff #define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG11_ACK 0x0700 #define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG12_ACK 0x0701 #define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG13_ACK 0x0702 #define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG14_ACK 0x0703 #define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG15_ACK 0x0704 #define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG16_ACK 0x0705 #define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG17_ACK 0x0706 #define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 // addressBlock: mmhub_utcl2_vml2pldec // base address: 0x69e90 #define mmMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 #define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 #define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 #define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 #define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 #define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER6_CFG 0x07aa #define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER7_CFG 0x07ab #define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 // addressBlock: mmhub_utcl2_vml2prdec // base address: 0x69ee0 #define mmMC_VM_L2_PERFCOUNTER_LO 0x07b8 #define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 #define mmMC_VM_L2_PERFCOUNTER_HI 0x07b9 #define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 // addressBlock: mmhub_utcl2_vmsharedhvdec // base address: 0x69f30 #define mmMC_VM_FB_SIZE_OFFSET_VF0 0x07cc #define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF1 0x07cd #define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF2 0x07ce #define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF3 0x07cf #define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 #define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 #define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 #define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 #define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 #define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 #define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 #define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 #define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 #define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 #define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF14 0x07da #define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 #define mmMC_VM_FB_SIZE_OFFSET_VF15 0x07db #define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 #define mmVM_IOMMU_MMIO_CNTRL_1 0x07dc #define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 #define mmMC_VM_MARC_BASE_LO_0 0x07dd #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 0 #define mmMC_VM_MARC_BASE_LO_1 0x07de #define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 0 #define mmMC_VM_MARC_BASE_LO_2 0x07df #define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 0 #define mmMC_VM_MARC_BASE_LO_3 0x07e0 #define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 0 #define mmMC_VM_MARC_BASE_HI_0 0x07e1 #define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 0 #define mmMC_VM_MARC_BASE_HI_1 0x07e2 #define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 0 #define mmMC_VM_MARC_BASE_HI_2 0x07e3 #define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 0 #define mmMC_VM_MARC_BASE_HI_3 0x07e4 #define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_LO_0 0x07e5 #define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_LO_1 0x07e6 #define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_LO_2 0x07e7 #define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_LO_3 0x07e8 #define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_HI_0 0x07e9 #define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_HI_1 0x07ea #define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_HI_2 0x07eb #define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 #define mmMC_VM_MARC_RELOC_HI_3 0x07ec #define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 #define mmMC_VM_MARC_LEN_LO_0 0x07ed #define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 0 #define mmMC_VM_MARC_LEN_LO_1 0x07ee #define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 0 #define mmMC_VM_MARC_LEN_LO_2 0x07ef #define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 0 #define mmMC_VM_MARC_LEN_LO_3 0x07f0 #define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 0 #define mmMC_VM_MARC_LEN_HI_0 0x07f1 #define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 0 #define mmMC_VM_MARC_LEN_HI_1 0x07f2 #define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 0 #define mmMC_VM_MARC_LEN_HI_2 0x07f3 #define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 0 #define mmMC_VM_MARC_LEN_HI_3 0x07f4 #define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 0 #define mmVM_IOMMU_CONTROL_REGISTER 0x07f5 #define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 #define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07f6 #define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL 0x07f7 #define mmVM_PCIE_ATS_CNTL_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_0 0x07f8 #define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_1 0x07f9 #define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_2 0x07fa #define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_3 0x07fb #define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_4 0x07fc #define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_5 0x07fd #define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_6 0x07fe #define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_7 0x07ff #define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_8 0x0800 #define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_9 0x0801 #define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_10 0x0802 #define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_11 0x0803 #define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_12 0x0804 #define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_13 0x0805 #define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_14 0x0806 #define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 #define mmVM_PCIE_ATS_CNTL_VF_15 0x0807 #define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 #define mmUTCL2_CGTT_CLK_CTRL 0x0808 #define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 // addressBlock: mmhub_utcl2_vmsharedpfdec // base address: 0x6a040 #define mmMC_VM_NB_MMIOBASE 0x0810 #define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 #define mmMC_VM_NB_MMIOLIMIT 0x0811 #define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 #define mmMC_VM_NB_PCI_CTRL 0x0812 #define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 #define mmMC_VM_NB_PCI_ARB 0x0813 #define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0814 #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0815 #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0816 #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 #define mmMC_VM_FB_OFFSET 0x0817 #define mmMC_VM_FB_OFFSET_BASE_IDX 0 #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0818 #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0819 #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 #define mmMC_VM_STEERING 0x081a #define mmMC_VM_STEERING_BASE_IDX 0 #define mmMC_SHARED_VIRT_RESET_REQ 0x081b #define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 #define mmMC_MEM_POWER_LS 0x081c #define mmMC_MEM_POWER_LS_BASE_IDX 0 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x081d #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x081e #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 #define mmMC_VM_APT_CNTL 0x081f #define mmMC_VM_APT_CNTL_BASE_IDX 0 #define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0820 #define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 #define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0821 #define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 #define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0822 #define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 // addressBlock: mmhub_utcl2_vmsharedvcdec // base address: 0x6a0b0 #define mmMC_VM_FB_LOCATION_BASE 0x082c #define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 #define mmMC_VM_FB_LOCATION_TOP 0x082d #define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 #define mmMC_VM_AGP_TOP 0x082e #define mmMC_VM_AGP_TOP_BASE_IDX 0 #define mmMC_VM_AGP_BOT 0x082f #define mmMC_VM_AGP_BOT_BASE_IDX 0 #define mmMC_VM_AGP_BASE 0x0830 #define mmMC_VM_AGP_BASE_BASE_IDX 0 #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0831 #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0832 #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 #define mmMC_VM_MX_L1_TLB_CNTL 0x0833 #define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 // addressBlock: mmhub_utcl2_atcl2pfcntrdec // base address: 0x6a100 #define mmATC_L2_PERFCOUNTER_LO 0x0840 #define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 0 #define mmATC_L2_PERFCOUNTER_HI 0x0841 #define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 0 // addressBlock: mmhub_utcl2_atcl2pfcntldec // base address: 0x6a120 #define mmATC_L2_PERFCOUNTER0_CFG 0x0848 #define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 #define mmATC_L2_PERFCOUNTER1_CFG 0x0849 #define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 #define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 #endif
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