Author | Tokens | Token Proportion | Commits | Commit Proportion |
---|---|---|---|---|
Yong Wu | 1236 | 65.96% | 3 | 37.50% |
Honghui Zhang | 616 | 32.87% | 3 | 37.50% |
Arvind Yadav | 12 | 0.64% | 1 | 12.50% |
Philipp Zabel | 10 | 0.53% | 1 | 12.50% |
Total | 1874 | 8 |
/* * Copyright (c) 2015-2016 MediaTek Inc. * Author: Yong Wu <yong.wu@mediatek.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/clk.h> #include <linux/component.h> #include <linux/device.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <soc/mediatek/smi.h> #include <dt-bindings/memory/mt2701-larb-port.h> /* mt8173 */ #define SMI_LARB_MMU_EN 0xf00 /* mt2701 */ #define REG_SMI_SECUR_CON_BASE 0x5c0 /* every register control 8 port, register offset 0x4 */ #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) #define REG_SMI_SECUR_CON_ADDR(id) \ (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) /* * every port have 4 bit to control, bit[port + 3] control virtual or physical, * bit[port + 2 : port + 1] control the domain, bit[port] control the security * or non-security. */ #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) /* mt2701 domain should be set to 3 */ #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) /* mt2712 */ #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) #define F_MMU_EN BIT(0) struct mtk_smi_larb_gen { bool need_larbid; int port_in_larb[MTK_LARB_NR_MAX + 1]; void (*config_port)(struct device *); }; struct mtk_smi { struct device *dev; struct clk *clk_apb, *clk_smi; struct clk *clk_async; /*only needed by mt2701*/ void __iomem *smi_ao_base; }; struct mtk_smi_larb { /* larb: local arbiter */ struct mtk_smi smi; void __iomem *base; struct device *smi_common_dev; const struct mtk_smi_larb_gen *larb_gen; int larbid; u32 *mmu; }; enum mtk_smi_gen { MTK_SMI_GEN1, MTK_SMI_GEN2 }; static int mtk_smi_enable(const struct mtk_smi *smi) { int ret; ret = pm_runtime_get_sync(smi->dev); if (ret < 0) return ret; ret = clk_prepare_enable(smi->clk_apb); if (ret) goto err_put_pm; ret = clk_prepare_enable(smi->clk_smi); if (ret) goto err_disable_apb; return 0; err_disable_apb: clk_disable_unprepare(smi->clk_apb); err_put_pm: pm_runtime_put_sync(smi->dev); return ret; } static void mtk_smi_disable(const struct mtk_smi *smi) { clk_disable_unprepare(smi->clk_smi); clk_disable_unprepare(smi->clk_apb); pm_runtime_put_sync(smi->dev); } int mtk_smi_larb_get(struct device *larbdev) { struct mtk_smi_larb *larb = dev_get_drvdata(larbdev); const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); int ret; /* Enable the smi-common's power and clocks */ ret = mtk_smi_enable(common); if (ret) return ret; /* Enable the larb's power and clocks */ ret = mtk_smi_enable(&larb->smi); if (ret) { mtk_smi_disable(common); return ret; } /* Configure the iommu info for this larb */ larb_gen->config_port(larbdev); return 0; } EXPORT_SYMBOL_GPL(mtk_smi_larb_get); void mtk_smi_larb_put(struct device *larbdev) { struct mtk_smi_larb *larb = dev_get_drvdata(larbdev); struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); /* * Don't de-configure the iommu info for this larb since there may be * several modules in this larb. * The iommu info will be reset after power off. */ mtk_smi_disable(&larb->smi); mtk_smi_disable(common); } EXPORT_SYMBOL_GPL(mtk_smi_larb_put); static int mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); struct mtk_smi_iommu *smi_iommu = data; unsigned int i; if (larb->larb_gen->need_larbid) { larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu; return 0; } /* * If there is no larbid property, Loop to find the corresponding * iommu information. */ for (i = 0; i < smi_iommu->larb_nr; i++) { if (dev == smi_iommu->larb_imu[i].dev) { /* The 'mmu' may be updated in iommu-attach/detach. */ larb->mmu = &smi_iommu->larb_imu[i].mmu; return 0; } } return -ENODEV; } static void mtk_smi_larb_config_port_mt2712(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); u32 reg; int i; /* * larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly. * Don't need to set it again. */ if (larb->larbid == 8 || larb->larbid == 9) return; for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); reg |= F_MMU_EN; writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); } } static void mtk_smi_larb_config_port_mt8173(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN); } static void mtk_smi_larb_config_port_gen1(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); int i, m4u_port_id, larb_port_num; u32 sec_con_val, reg_val; m4u_port_id = larb_gen->port_in_larb[larb->larbid]; larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] - larb_gen->port_in_larb[larb->larbid]; for (i = 0; i < larb_port_num; i++, m4u_port_id++) { if (*larb->mmu & BIT(i)) { /* bit[port + 3] controls the virtual or physical */ sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); } else { /* do not need to enable m4u for this port */ continue; } reg_val = readl(common->smi_ao_base + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); reg_val |= sec_con_val; reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); writel(reg_val, common->smi_ao_base + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); } } static void mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) { /* Do nothing as the iommu is always enabled. */ } static const struct component_ops mtk_smi_larb_component_ops = { .bind = mtk_smi_larb_bind, .unbind = mtk_smi_larb_unbind, }; static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { /* mt8173 do not need the port in larb */ .config_port = mtk_smi_larb_config_port_mt8173, }; static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { .need_larbid = true, .port_in_larb = { LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, LARB2_PORT_OFFSET, LARB3_PORT_OFFSET }, .config_port = mtk_smi_larb_config_port_gen1, }; static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { .need_larbid = true, .config_port = mtk_smi_larb_config_port_mt2712, }; static const struct of_device_id mtk_smi_larb_of_ids[] = { { .compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173 }, { .compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701 }, { .compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712 }, {} }; static int mtk_smi_larb_probe(struct platform_device *pdev) { struct mtk_smi_larb *larb; struct resource *res; struct device *dev = &pdev->dev; struct device_node *smi_node; struct platform_device *smi_pdev; int err; larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); if (!larb) return -ENOMEM; larb->larb_gen = of_device_get_match_data(dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); larb->base = devm_ioremap_resource(dev, res); if (IS_ERR(larb->base)) return PTR_ERR(larb->base); larb->smi.clk_apb = devm_clk_get(dev, "apb"); if (IS_ERR(larb->smi.clk_apb)) return PTR_ERR(larb->smi.clk_apb); larb->smi.clk_smi = devm_clk_get(dev, "smi"); if (IS_ERR(larb->smi.clk_smi)) return PTR_ERR(larb->smi.clk_smi); larb->smi.dev = dev; if (larb->larb_gen->need_larbid) { err = of_property_read_u32(dev->of_node, "mediatek,larb-id", &larb->larbid); if (err) { dev_err(dev, "missing larbid property\n"); return err; } } smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); if (!smi_node) return -EINVAL; smi_pdev = of_find_device_by_node(smi_node); of_node_put(smi_node); if (smi_pdev) { if (!platform_get_drvdata(smi_pdev)) return -EPROBE_DEFER; larb->smi_common_dev = &smi_pdev->dev; } else { dev_err(dev, "Failed to get the smi_common device\n"); return -EINVAL; } pm_runtime_enable(dev); platform_set_drvdata(pdev, larb); return component_add(dev, &mtk_smi_larb_component_ops); } static int mtk_smi_larb_remove(struct platform_device *pdev) { pm_runtime_disable(&pdev->dev); component_del(&pdev->dev, &mtk_smi_larb_component_ops); return 0; } static struct platform_driver mtk_smi_larb_driver = { .probe = mtk_smi_larb_probe, .remove = mtk_smi_larb_remove, .driver = { .name = "mtk-smi-larb", .of_match_table = mtk_smi_larb_of_ids, } }; static const struct of_device_id mtk_smi_common_of_ids[] = { { .compatible = "mediatek,mt8173-smi-common", .data = (void *)MTK_SMI_GEN2 }, { .compatible = "mediatek,mt2701-smi-common", .data = (void *)MTK_SMI_GEN1 }, { .compatible = "mediatek,mt2712-smi-common", .data = (void *)MTK_SMI_GEN2 }, {} }; static int mtk_smi_common_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_smi *common; struct resource *res; enum mtk_smi_gen smi_gen; int ret; common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); if (!common) return -ENOMEM; common->dev = dev; common->clk_apb = devm_clk_get(dev, "apb"); if (IS_ERR(common->clk_apb)) return PTR_ERR(common->clk_apb); common->clk_smi = devm_clk_get(dev, "smi"); if (IS_ERR(common->clk_smi)) return PTR_ERR(common->clk_smi); /* * for mtk smi gen 1, we need to get the ao(always on) base to config * m4u port, and we need to enable the aync clock for transform the smi * clock into emi clock domain, but for mtk smi gen2, there's no smi ao * base. */ smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev); if (smi_gen == MTK_SMI_GEN1) { res = platform_get_resource(pdev, IORESOURCE_MEM, 0); common->smi_ao_base = devm_ioremap_resource(dev, res); if (IS_ERR(common->smi_ao_base)) return PTR_ERR(common->smi_ao_base); common->clk_async = devm_clk_get(dev, "async"); if (IS_ERR(common->clk_async)) return PTR_ERR(common->clk_async); ret = clk_prepare_enable(common->clk_async); if (ret) return ret; } pm_runtime_enable(dev); platform_set_drvdata(pdev, common); return 0; } static int mtk_smi_common_remove(struct platform_device *pdev) { pm_runtime_disable(&pdev->dev); return 0; } static struct platform_driver mtk_smi_common_driver = { .probe = mtk_smi_common_probe, .remove = mtk_smi_common_remove, .driver = { .name = "mtk-smi-common", .of_match_table = mtk_smi_common_of_ids, } }; static int __init mtk_smi_init(void) { int ret; ret = platform_driver_register(&mtk_smi_common_driver); if (ret != 0) { pr_err("Failed to register SMI driver\n"); return ret; } ret = platform_driver_register(&mtk_smi_larb_driver); if (ret != 0) { pr_err("Failed to register SMI-LARB driver\n"); goto err_unreg_smi; } return ret; err_unreg_smi: platform_driver_unregister(&mtk_smi_common_driver); return ret; } module_init(mtk_smi_init);
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