Contributors: 10
Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
Tvrtko A. Ursulin |
131 |
27.58% |
10 |
37.04% |
Daniele Ceraolo Spurio |
106 |
22.32% |
4 |
14.81% |
Chris Wilson |
71 |
14.95% |
4 |
14.81% |
Michał Winiarski |
58 |
12.21% |
2 |
7.41% |
Andi Shyti |
36 |
7.58% |
1 |
3.70% |
Matt Roper |
36 |
7.58% |
1 |
3.70% |
Matthew Brost |
12 |
2.53% |
1 |
3.70% |
Venkata Sandeep Dhanalakota |
10 |
2.11% |
2 |
7.41% |
Matthew Auld |
9 |
1.89% |
1 |
3.70% |
Lionel Landwerlin |
6 |
1.26% |
1 |
3.70% |
Total |
475 |
|
27 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2019 Intel Corporation
*/
#ifndef __INTEL_GT__
#define __INTEL_GT__
#include "intel_engine_types.h"
#include "intel_gt_types.h"
#include "intel_reset.h"
struct drm_i915_private;
struct drm_printer;
#define GT_TRACE(gt, fmt, ...) do { \
const struct intel_gt *gt__ __maybe_unused = (gt); \
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
##__VA_ARGS__); \
} while (0)
static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
{
return container_of(uc, struct intel_gt, uc);
}
static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
{
return container_of(guc, struct intel_gt, uc.guc);
}
static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
{
return container_of(huc, struct intel_gt, uc.huc);
}
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
int intel_gt_probe_lmem(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
int intel_gt_init(struct intel_gt *gt);
void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
void intel_gt_driver_late_release(struct intel_gt *gt);
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
void intel_gt_check_and_clear_faults(struct intel_gt *gt);
void intel_gt_clear_error_registers(struct intel_gt *gt,
intel_engine_mask_t engine_mask);
void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
void intel_gt_chipset_flush(struct intel_gt *gt);
static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
enum intel_gt_scratch_field field)
{
return i915_ggtt_offset(gt->scratch) + field;
}
static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt)
{
return test_bit(I915_WEDGED_ON_INIT, >->reset.flags) ||
test_bit(I915_WEDGED_ON_FINI, >->reset.flags);
}
static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
{
GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) &&
!test_bit(I915_WEDGED, >->reset.flags));
return unlikely(test_bit(I915_WEDGED, >->reset.flags));
}
static inline bool intel_gt_needs_read_steering(struct intel_gt *gt,
enum intel_steering_type type)
{
return gt->steering_table[type];
}
u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
void intel_gt_watchdog_work(struct work_struct *work);
void intel_gt_invalidate_tlbs(struct intel_gt *gt);
#endif /* __INTEL_GT_H__ */