/* SPDX-License-Identifier: GPL-2.0 */ /* * DPAA2 Ethernet Switch declarations * * Copyright 2014-2016 Freescale Semiconductor Inc. * Copyright 2017-2018 NXP * */ #ifndef __ETHSW_H #define __ETHSW_H #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/rtnetlink.h> #include <linux/if_vlan.h> #include <uapi/linux/if_bridge.h> #include <net/switchdev.h> #include <linux/if_bridge.h> #include "dpsw.h" /* Number of IRQs supported */ #define DPSW_IRQ_NUM 2 #define ETHSW_VLAN_MEMBER 1 #define ETHSW_VLAN_UNTAGGED 2 #define ETHSW_VLAN_PVID 4 #define ETHSW_VLAN_GLOBAL 8 /* Maximum Frame Length supported by HW (currently 10k) */ #define DPAA2_MFL (10 * 1024) #define ETHSW_MAX_FRAME_LENGTH (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN) #define ETHSW_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN) extern const struct ethtool_ops ethsw_port_ethtool_ops; struct ethsw_core; /* Per port private data */ struct ethsw_port_priv { struct net_device *netdev; u16 idx; struct ethsw_core *ethsw_data; u8 link_state; u8 stp_state; bool flood; u8 vlans[VLAN_VID_MASK + 1]; u16 pvid; struct net_device *bridge_dev; }; /* Switch data */ struct ethsw_core { struct device *dev; struct fsl_mc_io *mc_io; u16 dpsw_handle; struct dpsw_attr sw_attr; int dev_id; struct ethsw_port_priv **ports; u8 vlans[VLAN_VID_MASK + 1]; bool learning; }; #endif /* __ETHSW_H */