| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Alex Deucher | 1203 | 100.00% | 1 | 100.00% |
| Total | 1203 | 1 |
/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _osssys_4_0_OFFSET_HEADER #define _osssys_4_0_OFFSET_HEADER // addressBlock: osssys_osssysdec // base address: 0x4280 #define mmIH_VMID_0_LUT 0x0000 #define mmIH_VMID_0_LUT_BASE_IDX 0 #define mmIH_VMID_1_LUT 0x0001 #define mmIH_VMID_1_LUT_BASE_IDX 0 #define mmIH_VMID_2_LUT 0x0002 #define mmIH_VMID_2_LUT_BASE_IDX 0 #define mmIH_VMID_3_LUT 0x0003 #define mmIH_VMID_3_LUT_BASE_IDX 0 #define mmIH_VMID_4_LUT 0x0004 #define mmIH_VMID_4_LUT_BASE_IDX 0 #define mmIH_VMID_5_LUT 0x0005 #define mmIH_VMID_5_LUT_BASE_IDX 0 #define mmIH_VMID_6_LUT 0x0006 #define mmIH_VMID_6_LUT_BASE_IDX 0 #define mmIH_VMID_7_LUT 0x0007 #define mmIH_VMID_7_LUT_BASE_IDX 0 #define mmIH_VMID_8_LUT 0x0008 #define mmIH_VMID_8_LUT_BASE_IDX 0 #define mmIH_VMID_9_LUT 0x0009 #define mmIH_VMID_9_LUT_BASE_IDX 0 #define mmIH_VMID_10_LUT 0x000a #define mmIH_VMID_10_LUT_BASE_IDX 0 #define mmIH_VMID_11_LUT 0x000b #define mmIH_VMID_11_LUT_BASE_IDX 0 #define mmIH_VMID_12_LUT 0x000c #define mmIH_VMID_12_LUT_BASE_IDX 0 #define mmIH_VMID_13_LUT 0x000d #define mmIH_VMID_13_LUT_BASE_IDX 0 #define mmIH_VMID_14_LUT 0x000e #define mmIH_VMID_14_LUT_BASE_IDX 0 #define mmIH_VMID_15_LUT 0x000f #define mmIH_VMID_15_LUT_BASE_IDX 0 #define mmIH_VMID_0_LUT_MM 0x0010 #define mmIH_VMID_0_LUT_MM_BASE_IDX 0 #define mmIH_VMID_1_LUT_MM 0x0011 #define mmIH_VMID_1_LUT_MM_BASE_IDX 0 #define mmIH_VMID_2_LUT_MM 0x0012 #define mmIH_VMID_2_LUT_MM_BASE_IDX 0 #define mmIH_VMID_3_LUT_MM 0x0013 #define mmIH_VMID_3_LUT_MM_BASE_IDX 0 #define mmIH_VMID_4_LUT_MM 0x0014 #define mmIH_VMID_4_LUT_MM_BASE_IDX 0 #define mmIH_VMID_5_LUT_MM 0x0015 #define mmIH_VMID_5_LUT_MM_BASE_IDX 0 #define mmIH_VMID_6_LUT_MM 0x0016 #define mmIH_VMID_6_LUT_MM_BASE_IDX 0 #define mmIH_VMID_7_LUT_MM 0x0017 #define mmIH_VMID_7_LUT_MM_BASE_IDX 0 #define mmIH_VMID_8_LUT_MM 0x0018 #define mmIH_VMID_8_LUT_MM_BASE_IDX 0 #define mmIH_VMID_9_LUT_MM 0x0019 #define mmIH_VMID_9_LUT_MM_BASE_IDX 0 #define mmIH_VMID_10_LUT_MM 0x001a #define mmIH_VMID_10_LUT_MM_BASE_IDX 0 #define mmIH_VMID_11_LUT_MM 0x001b #define mmIH_VMID_11_LUT_MM_BASE_IDX 0 #define mmIH_VMID_12_LUT_MM 0x001c #define mmIH_VMID_12_LUT_MM_BASE_IDX 0 #define mmIH_VMID_13_LUT_MM 0x001d #define mmIH_VMID_13_LUT_MM_BASE_IDX 0 #define mmIH_VMID_14_LUT_MM 0x001e #define mmIH_VMID_14_LUT_MM_BASE_IDX 0 #define mmIH_VMID_15_LUT_MM 0x001f #define mmIH_VMID_15_LUT_MM_BASE_IDX 0 #define mmIH_COOKIE_0 0x0020 #define mmIH_COOKIE_0_BASE_IDX 0 #define mmIH_COOKIE_1 0x0021 #define mmIH_COOKIE_1_BASE_IDX 0 #define mmIH_COOKIE_2 0x0022 #define mmIH_COOKIE_2_BASE_IDX 0 #define mmIH_COOKIE_3 0x0023 #define mmIH_COOKIE_3_BASE_IDX 0 #define mmIH_COOKIE_4 0x0024 #define mmIH_COOKIE_4_BASE_IDX 0 #define mmIH_COOKIE_5 0x0025 #define mmIH_COOKIE_5_BASE_IDX 0 #define mmIH_COOKIE_6 0x0026 #define mmIH_COOKIE_6_BASE_IDX 0 #define mmIH_COOKIE_7 0x0027 #define mmIH_COOKIE_7_BASE_IDX 0 #define mmIH_REGISTER_LAST_PART0 0x003f #define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 #define mmSEM_REQ_INPUT_0 0x0040 #define mmSEM_REQ_INPUT_0_BASE_IDX 0 #define mmSEM_REQ_INPUT_1 0x0041 #define mmSEM_REQ_INPUT_1_BASE_IDX 0 #define mmSEM_REQ_INPUT_2 0x0042 #define mmSEM_REQ_INPUT_2_BASE_IDX 0 #define mmSEM_REQ_INPUT_3 0x0043 #define mmSEM_REQ_INPUT_3_BASE_IDX 0 #define mmSEM_REGISTER_LAST_PART0 0x007f #define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 #define mmIH_RB_CNTL 0x0080 #define mmIH_RB_CNTL_BASE_IDX 0 #define mmIH_RB_BASE 0x0081 #define mmIH_RB_BASE_BASE_IDX 0 #define mmIH_RB_BASE_HI 0x0082 #define mmIH_RB_BASE_HI_BASE_IDX 0 #define mmIH_RB_RPTR 0x0083 #define mmIH_RB_RPTR_BASE_IDX 0 #define mmIH_RB_WPTR 0x0084 #define mmIH_RB_WPTR_BASE_IDX 0 #define mmIH_RB_WPTR_ADDR_HI 0x0085 #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 #define mmIH_RB_WPTR_ADDR_LO 0x0086 #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 #define mmIH_DOORBELL_RPTR 0x0087 #define mmIH_DOORBELL_RPTR_BASE_IDX 0 #define mmIH_RB_CNTL_RING1 0x0088 #define mmIH_RB_CNTL_RING1_BASE_IDX 0 #define mmIH_RB_BASE_RING1 0x0089 #define mmIH_RB_BASE_RING1_BASE_IDX 0 #define mmIH_RB_BASE_HI_RING1 0x008a #define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 #define mmIH_RB_RPTR_RING1 0x008b #define mmIH_RB_RPTR_RING1_BASE_IDX 0 #define mmIH_RB_WPTR_RING1 0x008c #define mmIH_RB_WPTR_RING1_BASE_IDX 0 #define mmIH_DOORBELL_RPTR_RING1 0x008f #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 #define mmIH_RB_CNTL_RING2 0x0090 #define mmIH_RB_CNTL_RING2_BASE_IDX 0 #define mmIH_RB_BASE_RING2 0x0091 #define mmIH_RB_BASE_RING2_BASE_IDX 0 #define mmIH_RB_BASE_HI_RING2 0x0092 #define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 #define mmIH_RB_RPTR_RING2 0x0093 #define mmIH_RB_RPTR_RING2_BASE_IDX 0 #define mmIH_RB_WPTR_RING2 0x0094 #define mmIH_RB_WPTR_RING2_BASE_IDX 0 #define mmIH_DOORBELL_RPTR_RING2 0x0097 #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 #define mmIH_VERSION 0x0098 #define mmIH_VERSION_BASE_IDX 0 #define mmIH_CNTL 0x00c0 #define mmIH_CNTL_BASE_IDX 0 #define mmIH_CNTL2 0x00c1 #define mmIH_CNTL2_BASE_IDX 0 #define mmIH_STATUS 0x00c2 #define mmIH_STATUS_BASE_IDX 0 #define mmIH_PERFMON_CNTL 0x00c3 #define mmIH_PERFMON_CNTL_BASE_IDX 0 #define mmIH_PERFCOUNTER0_RESULT 0x00c4 #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 #define mmIH_PERFCOUNTER1_RESULT 0x00c5 #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 #define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 #define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 #define mmIH_DSM_MATCH_FCN_ID 0x00cc #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 #define mmIH_LIMIT_INT_RATE_CNTL 0x00cd #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 #define mmIH_VF_RB_STATUS 0x00ce #define mmIH_VF_RB_STATUS_BASE_IDX 0 #define mmIH_VF_RB_STATUS2 0x00cf #define mmIH_VF_RB_STATUS2_BASE_IDX 0 #define mmIH_VF_RB1_STATUS 0x00d0 #define mmIH_VF_RB1_STATUS_BASE_IDX 0 #define mmIH_VF_RB1_STATUS2 0x00d1 #define mmIH_VF_RB1_STATUS2_BASE_IDX 0 #define mmIH_VF_RB2_STATUS 0x00d2 #define mmIH_VF_RB2_STATUS_BASE_IDX 0 #define mmIH_VF_RB2_STATUS2 0x00d3 #define mmIH_VF_RB2_STATUS2_BASE_IDX 0 #define mmIH_INT_FLOOD_CNTL 0x00d5 #define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 #define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 #define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 #define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 #define mmIH_INT_FLOOD_STATUS 0x00d9 #define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 #define mmIH_STORM_CLIENT_LIST_CNTL 0x00da #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 #define mmIH_CLK_CTRL 0x00db #define mmIH_CLK_CTRL_BASE_IDX 0 #define mmIH_INT_FLAGS 0x00dc #define mmIH_INT_FLAGS_BASE_IDX 0 #define mmIH_LAST_INT_INFO0 0x00dd #define mmIH_LAST_INT_INFO0_BASE_IDX 0 #define mmIH_LAST_INT_INFO1 0x00de #define mmIH_LAST_INT_INFO1_BASE_IDX 0 #define mmIH_LAST_INT_INFO2 0x00df #define mmIH_LAST_INT_INFO2_BASE_IDX 0 #define mmIH_SCRATCH 0x00e0 #define mmIH_SCRATCH_BASE_IDX 0 #define mmIH_CLIENT_CREDIT_ERROR 0x00e1 #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 #define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 #define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3 #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 #define mmIH_CREDIT_STATUS 0x00e4 #define mmIH_CREDIT_STATUS_BASE_IDX 0 #define mmIH_MMHUB_ERROR 0x00e5 #define mmIH_MMHUB_ERROR_BASE_IDX 0 #define mmIH_REGISTER_LAST_PART2 0x00ff #define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 #define mmSEM_CLK_CTRL 0x0100 #define mmSEM_CLK_CTRL_BASE_IDX 0 #define mmSEM_UTC_CREDIT 0x0101 #define mmSEM_UTC_CREDIT_BASE_IDX 0 #define mmSEM_UTC_CONFIG 0x0102 #define mmSEM_UTC_CONFIG_BASE_IDX 0 #define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 #define mmSEM_MCIF_CONFIG 0x0104 #define mmSEM_MCIF_CONFIG_BASE_IDX 0 #define mmSEM_PERFMON_CNTL 0x0105 #define mmSEM_PERFMON_CNTL_BASE_IDX 0 #define mmSEM_PERFCOUNTER0_RESULT 0x0106 #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 #define mmSEM_PERFCOUNTER1_RESULT 0x0107 #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 #define mmSEM_STATUS 0x0108 #define mmSEM_STATUS_BASE_IDX 0 #define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 #define mmSEM_MAILBOX 0x010a #define mmSEM_MAILBOX_BASE_IDX 0 #define mmSEM_MAILBOX_CONTROL 0x010b #define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 #define mmSEM_CHICKEN_BITS 0x010c #define mmSEM_CHICKEN_BITS_BASE_IDX 0 #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 #define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 #define mmSEM_OUTSTANDING_THRESHOLD 0x010f #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 #define mmSEM_REGISTER_LAST_PART2 0x017f #define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 #define mmIH_ACTIVE_FCN_ID 0x0180 #define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 #define mmIH_VIRT_RESET_REQ 0x0181 #define mmIH_VIRT_RESET_REQ_BASE_IDX 0 #define mmIH_CLIENT_CFG 0x0184 #define mmIH_CLIENT_CFG_BASE_IDX 0 #define mmIH_CLIENT_CFG_INDEX 0x0188 #define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 #define mmIH_CLIENT_CFG_DATA 0x0189 #define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 #define mmIH_CID_REMAP_INDEX 0x018a #define mmIH_CID_REMAP_INDEX_BASE_IDX 0 #define mmIH_CID_REMAP_DATA 0x018b #define mmIH_CID_REMAP_DATA_BASE_IDX 0 #define mmIH_CHICKEN 0x018c #define mmIH_CHICKEN_BASE_IDX 0 #define mmIH_MMHUB_CNTL 0x018d #define mmIH_MMHUB_CNTL_BASE_IDX 0 #define mmIH_REGISTER_LAST_PART1 0x019f #define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 #define mmSEM_ACTIVE_FCN_ID 0x01a0 #define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 #define mmSEM_VIRT_RESET_REQ 0x01a1 #define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 #define mmSEM_RESP_SDMA0 0x01a4 #define mmSEM_RESP_SDMA0_BASE_IDX 0 #define mmSEM_RESP_SDMA1 0x01a5 #define mmSEM_RESP_SDMA1_BASE_IDX 0 #define mmSEM_RESP_UVD 0x01a6 #define mmSEM_RESP_UVD_BASE_IDX 0 #define mmSEM_RESP_VCE_0 0x01a7 #define mmSEM_RESP_VCE_0_BASE_IDX 0 #define mmSEM_RESP_ACP 0x01a8 #define mmSEM_RESP_ACP_BASE_IDX 0 #define mmSEM_RESP_ISP 0x01a9 #define mmSEM_RESP_ISP_BASE_IDX 0 #define mmSEM_RESP_VCE_1 0x01aa #define mmSEM_RESP_VCE_1_BASE_IDX 0 #define mmSEM_RESP_VP8 0x01ab #define mmSEM_RESP_VP8_BASE_IDX 0 #define mmSEM_RESP_GC 0x01ac #define mmSEM_RESP_GC_BASE_IDX 0 #define mmSEM_CID_REMAP_INDEX 0x01b0 #define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 #define mmSEM_CID_REMAP_DATA 0x01b1 #define mmSEM_CID_REMAP_DATA_BASE_IDX 0 #define mmSEM_ATOMIC_OP_LUT 0x01b2 #define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 #define mmSEM_EDC_CONFIG 0x01b3 #define mmSEM_EDC_CONFIG_BASE_IDX 0 #define mmSEM_CHICKEN_BITS2 0x01b4 #define mmSEM_CHICKEN_BITS2_BASE_IDX 0 #define mmSEM_MMHUB_CNTL 0x01b5 #define mmSEM_MMHUB_CNTL_BASE_IDX 0 #define mmSEM_REGISTER_LAST_PART1 0x01bf #define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 #endif
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