Author | Tokens | Token Proportion | Commits | Commit Proportion |
---|---|---|---|---|
Lionel Landwerlin | 874 | 100.00% | 1 | 100.00% |
Total | 874 | 1 |
// SPDX-License-Identifier: MIT /* * Copyright © 2018 Intel Corporation * * Autogenerated file by GPU Top : https://github.com/rib/gputop * DO NOT EDIT manually! */ #include <linux/sysfs.h> #include "i915_drv.h" #include "i915_oa_tgl.h" static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0xD920), 0x00000000 }, { _MMIO(0xD900), 0x00000000 }, { _MMIO(0xD904), 0xF0800000 }, { _MMIO(0xD910), 0x00000000 }, { _MMIO(0xD914), 0xF0800000 }, { _MMIO(0xDC40), 0x00FF0000 }, { _MMIO(0xD940), 0x00000004 }, { _MMIO(0xD944), 0x0000FFFF }, { _MMIO(0xDC00), 0x00000004 }, { _MMIO(0xDC04), 0x0000FFFF }, { _MMIO(0xD948), 0x00000003 }, { _MMIO(0xD94C), 0x0000FFFF }, { _MMIO(0xDC08), 0x00000003 }, { _MMIO(0xDC0C), 0x0000FFFF }, { _MMIO(0xD950), 0x00000007 }, { _MMIO(0xD954), 0x0000FFFF }, { _MMIO(0xDC10), 0x00000007 }, { _MMIO(0xDC14), 0x0000FFFF }, { _MMIO(0xD958), 0x00100002 }, { _MMIO(0xD95C), 0x0000FFF7 }, { _MMIO(0xDC18), 0x00100002 }, { _MMIO(0xDC1C), 0x0000FFF7 }, { _MMIO(0xD960), 0x00100002 }, { _MMIO(0xD964), 0x0000FFCF }, { _MMIO(0xDC20), 0x00100002 }, { _MMIO(0xDC24), 0x0000FFCF }, { _MMIO(0xD968), 0x00100082 }, { _MMIO(0xD96C), 0x0000FFEF }, { _MMIO(0xDC28), 0x00100082 }, { _MMIO(0xDC2C), 0x0000FFEF }, { _MMIO(0xD970), 0x001000C2 }, { _MMIO(0xD974), 0x0000FFE7 }, { _MMIO(0xDC30), 0x001000C2 }, { _MMIO(0xDC34), 0x0000FFE7 }, { _MMIO(0xD978), 0x00100001 }, { _MMIO(0xD97C), 0x0000FFE7 }, { _MMIO(0xDC38), 0x00100001 }, { _MMIO(0xDC3C), 0x0000FFE7 }, }; static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x0D04), 0x00000200 }, { _MMIO(0x9840), 0x00000000 }, { _MMIO(0x9884), 0x00000000 }, { _MMIO(0x9888), 0x280E0000 }, { _MMIO(0x9888), 0x1E0E0147 }, { _MMIO(0x9888), 0x180E0000 }, { _MMIO(0x9888), 0x160E0000 }, { _MMIO(0x9888), 0x1E0F1000 }, { _MMIO(0x9888), 0x1E104000 }, { _MMIO(0x9888), 0x2E020100 }, { _MMIO(0x9888), 0x2C030004 }, { _MMIO(0x9888), 0x38003000 }, { _MMIO(0x9888), 0x1E0A8000 }, { _MMIO(0x9884), 0x00000003 }, { _MMIO(0x9888), 0x49110000 }, { _MMIO(0x9888), 0x5D101400 }, { _MMIO(0x9888), 0x1D140020 }, { _MMIO(0x9888), 0x1D1103A3 }, { _MMIO(0x9888), 0x01110000 }, { _MMIO(0x9888), 0x61111000 }, { _MMIO(0x9888), 0x1F128000 }, { _MMIO(0x9888), 0x17100000 }, { _MMIO(0x9888), 0x55100630 }, { _MMIO(0x9888), 0x57100000 }, { _MMIO(0x9888), 0x31100000 }, { _MMIO(0x9884), 0x00000003 }, { _MMIO(0x9888), 0x65100002 }, { _MMIO(0x9884), 0x00000000 }, { _MMIO(0x9888), 0x42000001 }, }; static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { return sprintf(buf, "1\n"); } void i915_perf_load_test_config_tgl(struct drm_i915_private *dev_priv) { strlcpy(dev_priv->perf.test_config.uuid, "80a833f0-2504-4321-8894-e9277844ce7b", sizeof(dev_priv->perf.test_config.uuid)); dev_priv->perf.test_config.id = 1; dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv->perf.test_config.sysfs_metric.name = "80a833f0-2504-4321-8894-e9277844ce7b"; dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; }
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