Author | Tokens | Token Proportion | Commits | Commit Proportion |
---|---|---|---|---|
Heikki Krogerus | 906 | 29.80% | 24 | 28.92% |
Jamie Iles | 425 | 13.98% | 1 | 1.20% |
Noam Camus | 272 | 8.95% | 3 | 3.61% |
David Daney | 198 | 6.51% | 2 | 2.41% |
Andy Shevchenko | 176 | 5.79% | 12 | 14.46% |
Joshua Scott | 172 | 5.66% | 2 | 2.41% |
Tim Kryger | 164 | 5.39% | 2 | 2.41% |
Chen-Yu Tsai | 116 | 3.82% | 2 | 2.41% |
Ed Blake | 98 | 3.22% | 2 | 2.41% |
Doug Anderson | 94 | 3.09% | 1 | 1.20% |
Heiko Stübner | 92 | 3.03% | 2 | 2.41% |
James Hogan | 82 | 2.70% | 3 | 3.61% |
Emilio López | 72 | 2.37% | 1 | 1.20% |
Kefeng Wang | 29 | 0.95% | 4 | 4.82% |
Desmond Liu | 28 | 0.92% | 1 | 1.20% |
Qipeng Zha | 21 | 0.69% | 1 | 1.20% |
Mika Westerberg | 19 | 0.62% | 3 | 3.61% |
Alexey Brodkin | 10 | 0.33% | 1 | 1.20% |
Alan Cox | 9 | 0.30% | 2 | 2.41% |
Jason Uy | 8 | 0.26% | 1 | 1.20% |
Phil Edworthy | 7 | 0.23% | 1 | 1.20% |
Srinath Mannam <srinath.mannam@broadcom.com> | 6 | 0.20% | 1 | 1.20% |
Wang Hongcheng | 6 | 0.20% | 1 | 1.20% |
Ken Xue | 6 | 0.20% | 1 | 1.20% |
Feng Kan | 6 | 0.20% | 1 | 1.20% |
Stefan Potyra | 6 | 0.20% | 1 | 1.20% |
Philipp Zabel | 5 | 0.16% | 2 | 2.41% |
Julien CHAUVEAU | 3 | 0.10% | 1 | 1.20% |
Greg Kroah-Hartman | 2 | 0.07% | 2 | 2.41% |
Rafael J. Wysocki | 1 | 0.03% | 1 | 1.20% |
Axel Lin | 1 | 0.03% | 1 | 1.20% |
Total | 3040 | 83 |
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663
// SPDX-License-Identifier: GPL-2.0+ /* * Synopsys DesignWare 8250 driver. * * Copyright 2011 Picochip, Jamie Iles. * Copyright 2013 Intel Corporation * * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the * LCR is written whilst busy. If it is, then a busy detect interrupt is * raised, the LCR needs to be rewritten and the uart status register read. */ #include <linux/delay.h> #include <linux/device.h> #include <linux/io.h> #include <linux/module.h> #include <linux/serial_8250.h> #include <linux/serial_reg.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/acpi.h> #include <linux/clk.h> #include <linux/reset.h> #include <linux/pm_runtime.h> #include <asm/byteorder.h> #include "8250_dwlib.h" /* Offsets for the DesignWare specific registers */ #define DW_UART_USR 0x1f /* UART Status Register */ /* DesignWare specific register fields */ #define DW_UART_MCR_SIRE BIT(6) struct dw8250_data { struct dw8250_port_data data; u8 usr_reg; int msr_mask_on; int msr_mask_off; struct clk *clk; struct clk *pclk; struct reset_control *rst; unsigned int skip_autocfg:1; unsigned int uart_16550_compatible:1; }; static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) { return container_of(data, struct dw8250_data, data); } static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) { struct dw8250_data *d = to_dw8250_data(p->private_data); /* Override any modem control signals if needed */ if (offset == UART_MSR) { value |= d->msr_mask_on; value &= ~d->msr_mask_off; } return value; } static void dw8250_force_idle(struct uart_port *p) { struct uart_8250_port *up = up_to_u8250p(p); serial8250_clear_and_reinit_fifos(up); (void)p->serial_in(p, UART_RX); } static void dw8250_check_lcr(struct uart_port *p, int value) { void __iomem *offset = p->membase + (UART_LCR << p->regshift); int tries = 1000; /* Make sure LCR write wasn't ignored */ while (tries--) { unsigned int lcr = p->serial_in(p, UART_LCR); if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) return; dw8250_force_idle(p); #ifdef CONFIG_64BIT if (p->type == PORT_OCTEON) __raw_writeq(value & 0xff, offset); else #endif if (p->iotype == UPIO_MEM32) writel(value, offset); else if (p->iotype == UPIO_MEM32BE) iowrite32be(value, offset); else writeb(value, offset); } /* * FIXME: this deadlocks if port->lock is already held * dev_err(p->dev, "Couldn't set LCR to %d\n", value); */ } /* Returns once the transmitter is empty or we run out of retries */ static void dw8250_tx_wait_empty(struct uart_port *p) { unsigned int tries = 20000; unsigned int delay_threshold = tries - 1000; unsigned int lsr; while (tries--) { lsr = readb (p->membase + (UART_LSR << p->regshift)); if (lsr & UART_LSR_TEMT) break; /* The device is first given a chance to empty without delay, * to avoid slowdowns at high bitrates. If after 1000 tries * the buffer has still not emptied, allow more time for low- * speed links. */ if (tries < delay_threshold) udelay (1); } } static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) { struct dw8250_data *d = to_dw8250_data(p->private_data); /* Allow the TX to drain before we reconfigure */ if (offset == UART_LCR) dw8250_tx_wait_empty(p); writeb(value, p->membase + (offset << p->regshift)); if (offset == UART_LCR && !d->uart_16550_compatible) dw8250_check_lcr(p, value); } static void dw8250_serial_out(struct uart_port *p, int offset, int value) { struct dw8250_data *d = to_dw8250_data(p->private_data); writeb(value, p->membase + (offset << p->regshift)); if (offset == UART_LCR && !d->uart_16550_compatible) dw8250_check_lcr(p, value); } static unsigned int dw8250_serial_in(struct uart_port *p, int offset) { unsigned int value = readb(p->membase + (offset << p->regshift)); return dw8250_modify_msr(p, offset, value); } #ifdef CONFIG_64BIT static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) { unsigned int value; value = (u8)__raw_readq(p->membase + (offset << p->regshift)); return dw8250_modify_msr(p, offset, value); } static void dw8250_serial_outq(struct uart_port *p, int offset, int value) { struct dw8250_data *d = to_dw8250_data(p->private_data); value &= 0xff; __raw_writeq(value, p->membase + (offset << p->regshift)); /* Read back to ensure register write ordering. */ __raw_readq(p->membase + (UART_LCR << p->regshift)); if (offset == UART_LCR && !d->uart_16550_compatible) dw8250_check_lcr(p, value); } #endif /* CONFIG_64BIT */ static void dw8250_serial_out32(struct uart_port *p, int offset, int value) { struct dw8250_data *d = to_dw8250_data(p->private_data); writel(value, p->membase + (offset << p->regshift)); if (offset == UART_LCR && !d->uart_16550_compatible) dw8250_check_lcr(p, value); } static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) { unsigned int value = readl(p->membase + (offset << p->regshift)); return dw8250_modify_msr(p, offset, value); } static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) { struct dw8250_data *d = to_dw8250_data(p->private_data); iowrite32be(value, p->membase + (offset << p->regshift)); if (offset == UART_LCR && !d->uart_16550_compatible) dw8250_check_lcr(p, value); } static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) { unsigned int value = ioread32be(p->membase + (offset << p->regshift)); return dw8250_modify_msr(p, offset, value); } static int dw8250_handle_irq(struct uart_port *p) { struct uart_8250_port *up = up_to_u8250p(p); struct dw8250_data *d = to_dw8250_data(p->private_data); unsigned int iir = p->serial_in(p, UART_IIR); unsigned int status; unsigned long flags; /* * There are ways to get Designware-based UARTs into a state where * they are asserting UART_IIR_RX_TIMEOUT but there is no actual * data available. If we see such a case then we'll do a bogus * read. If we don't do this then the "RX TIMEOUT" interrupt will * fire forever. * * This problem has only been observed so far when not in DMA mode * so we limit the workaround only to non-DMA mode. */ if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { spin_lock_irqsave(&p->lock, flags); status = p->serial_in(p, UART_LSR); if (!(status & (UART_LSR_DR | UART_LSR_BI))) (void) p->serial_in(p, UART_RX); spin_unlock_irqrestore(&p->lock, flags); } if (serial8250_handle_irq(p, iir)) return 1; if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { /* Clear the USR */ (void)p->serial_in(p, d->usr_reg); return 1; } return 0; } static void dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) { if (!state) pm_runtime_get_sync(port->dev); serial8250_do_pm(port, state, old); if (state) pm_runtime_put_sync_suspend(port->dev); } static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old) { unsigned int baud = tty_termios_baud_rate(termios); struct dw8250_data *d = to_dw8250_data(p->private_data); long rate; int ret; clk_disable_unprepare(d->clk); rate = clk_round_rate(d->clk, baud * 16); if (rate < 0) ret = rate; else if (rate == 0) ret = -ENOENT; else ret = clk_set_rate(d->clk, rate); clk_prepare_enable(d->clk); if (ret) goto out; p->uartclk = rate; out: p->status &= ~UPSTAT_AUTOCTS; if (termios->c_cflag & CRTSCTS) p->status |= UPSTAT_AUTOCTS; serial8250_do_set_termios(p, termios, old); } static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) { struct uart_8250_port *up = up_to_u8250p(p); unsigned int mcr = p->serial_in(p, UART_MCR); if (up->capabilities & UART_CAP_IRDA) { if (termios->c_line == N_IRDA) mcr |= DW_UART_MCR_SIRE; else mcr &= ~DW_UART_MCR_SIRE; p->serial_out(p, UART_MCR, mcr); } serial8250_do_set_ldisc(p, termios); } /* * dw8250_fallback_dma_filter will prevent the UART from getting just any free * channel on platforms that have DMA engines, but don't have any channels * assigned to the UART. * * REVISIT: This is a work around for limitation in the DMA Engine API. Once the * core problem is fixed, this function is no longer needed. */ static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) { return false; } static bool dw8250_idma_filter(struct dma_chan *chan, void *param) { return param == chan->device->dev; } static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { if (p->dev->of_node) { struct device_node *np = p->dev->of_node; int id; /* get index of serial line, if found in DT aliases */ id = of_alias_get_id(np, "serial"); if (id >= 0) p->line = id; #ifdef CONFIG_64BIT if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { p->serial_in = dw8250_serial_inq; p->serial_out = dw8250_serial_outq; p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; p->type = PORT_OCTEON; data->usr_reg = 0x27; data->skip_autocfg = true; } #endif if (of_device_is_big_endian(p->dev->of_node)) { p->iotype = UPIO_MEM32BE; p->serial_in = dw8250_serial_in32be; p->serial_out = dw8250_serial_out32be; } if (of_device_is_compatible(np, "marvell,armada-38x-uart")) p->serial_out = dw8250_serial_out38x; } else if (acpi_dev_present("APMC0D08", NULL, -1)) { p->iotype = UPIO_MEM32; p->regshift = 2; p->serial_in = dw8250_serial_in32; data->uart_16550_compatible = true; } /* Platforms with iDMA 64-bit */ if (platform_get_resource_byname(to_platform_device(p->dev), IORESOURCE_MEM, "lpss_priv")) { data->data.dma.rx_param = p->dev->parent; data->data.dma.tx_param = p->dev->parent; data->data.dma.fn = dw8250_idma_filter; } } static int dw8250_probe(struct platform_device *pdev) { struct uart_8250_port uart = {}, *up = &uart; struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); struct uart_port *p = &up->port; struct device *dev = &pdev->dev; struct dw8250_data *data; int irq; int err; u32 val; if (!regs) { dev_err(dev, "no registers defined\n"); return -EINVAL; } irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; spin_lock_init(&p->lock); p->mapbase = regs->start; p->irq = irq; p->handle_irq = dw8250_handle_irq; p->pm = dw8250_do_pm; p->type = PORT_8250; p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; p->dev = dev; p->iotype = UPIO_MEM; p->serial_in = dw8250_serial_in; p->serial_out = dw8250_serial_out; p->set_ldisc = dw8250_set_ldisc; p->set_termios = dw8250_set_termios; p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); if (!p->membase) return -ENOMEM; data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; data->data.dma.fn = dw8250_fallback_dma_filter; data->usr_reg = DW_UART_USR; p->private_data = &data->data; data->uart_16550_compatible = device_property_read_bool(dev, "snps,uart-16550-compatible"); err = device_property_read_u32(dev, "reg-shift", &val); if (!err) p->regshift = val; err = device_property_read_u32(dev, "reg-io-width", &val); if (!err && val == 4) { p->iotype = UPIO_MEM32; p->serial_in = dw8250_serial_in32; p->serial_out = dw8250_serial_out32; } if (device_property_read_bool(dev, "dcd-override")) { /* Always report DCD as active */ data->msr_mask_on |= UART_MSR_DCD; data->msr_mask_off |= UART_MSR_DDCD; } if (device_property_read_bool(dev, "dsr-override")) { /* Always report DSR as active */ data->msr_mask_on |= UART_MSR_DSR; data->msr_mask_off |= UART_MSR_DDSR; } if (device_property_read_bool(dev, "cts-override")) { /* Always report CTS as active */ data->msr_mask_on |= UART_MSR_CTS; data->msr_mask_off |= UART_MSR_DCTS; } if (device_property_read_bool(dev, "ri-override")) { /* Always report Ring indicator as inactive */ data->msr_mask_off |= UART_MSR_RI; data->msr_mask_off |= UART_MSR_TERI; } /* Always ask for fixed clock rate from a property. */ device_property_read_u32(dev, "clock-frequency", &p->uartclk); /* If there is separate baudclk, get the rate from it. */ data->clk = devm_clk_get_optional(dev, "baudclk"); if (data->clk == NULL) data->clk = devm_clk_get_optional(dev, NULL); if (IS_ERR(data->clk)) return PTR_ERR(data->clk); err = clk_prepare_enable(data->clk); if (err) dev_warn(dev, "could not enable optional baudclk: %d\n", err); if (data->clk) p->uartclk = clk_get_rate(data->clk); /* If no clock rate is defined, fail. */ if (!p->uartclk) { dev_err(dev, "clock rate not defined\n"); err = -EINVAL; goto err_clk; } data->pclk = devm_clk_get_optional(dev, "apb_pclk"); if (IS_ERR(data->pclk)) { err = PTR_ERR(data->pclk); goto err_clk; } err = clk_prepare_enable(data->pclk); if (err) { dev_err(dev, "could not enable apb_pclk\n"); goto err_clk; } data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); if (IS_ERR(data->rst)) { err = PTR_ERR(data->rst); goto err_pclk; } reset_control_deassert(data->rst); dw8250_quirks(p, data); /* If the Busy Functionality is not implemented, don't handle it */ if (data->uart_16550_compatible) p->handle_irq = NULL; if (!data->skip_autocfg) dw8250_setup_port(p); /* If we have a valid fifosize, try hooking up DMA */ if (p->fifosize) { data->data.dma.rxconf.src_maxburst = p->fifosize / 4; data->data.dma.txconf.dst_maxburst = p->fifosize / 4; up->dma = &data->data.dma; } data->data.line = serial8250_register_8250_port(up); if (data->data.line < 0) { err = data->data.line; goto err_reset; } platform_set_drvdata(pdev, data); pm_runtime_set_active(dev); pm_runtime_enable(dev); return 0; err_reset: reset_control_assert(data->rst); err_pclk: clk_disable_unprepare(data->pclk); err_clk: clk_disable_unprepare(data->clk); return err; } static int dw8250_remove(struct platform_device *pdev) { struct dw8250_data *data = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; pm_runtime_get_sync(dev); serial8250_unregister_port(data->data.line); reset_control_assert(data->rst); clk_disable_unprepare(data->pclk); clk_disable_unprepare(data->clk); pm_runtime_disable(dev); pm_runtime_put_noidle(dev); return 0; } #ifdef CONFIG_PM_SLEEP static int dw8250_suspend(struct device *dev) { struct dw8250_data *data = dev_get_drvdata(dev); serial8250_suspend_port(data->data.line); return 0; } static int dw8250_resume(struct device *dev) { struct dw8250_data *data = dev_get_drvdata(dev); serial8250_resume_port(data->data.line); return 0; } #endif /* CONFIG_PM_SLEEP */ #ifdef CONFIG_PM static int dw8250_runtime_suspend(struct device *dev) { struct dw8250_data *data = dev_get_drvdata(dev); clk_disable_unprepare(data->clk); clk_disable_unprepare(data->pclk); return 0; } static int dw8250_runtime_resume(struct device *dev) { struct dw8250_data *data = dev_get_drvdata(dev); clk_prepare_enable(data->pclk); clk_prepare_enable(data->clk); return 0; } #endif static const struct dev_pm_ops dw8250_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) }; static const struct of_device_id dw8250_of_match[] = { { .compatible = "snps,dw-apb-uart" }, { .compatible = "cavium,octeon-3860-uart" }, { .compatible = "marvell,armada-38x-uart" }, { .compatible = "renesas,rzn1-uart" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); static const struct acpi_device_id dw8250_acpi_match[] = { { "INT33C4", 0 }, { "INT33C5", 0 }, { "INT3434", 0 }, { "INT3435", 0 }, { "80860F0A", 0 }, { "8086228A", 0 }, { "APMC0D08", 0}, { "AMD0020", 0 }, { "AMDI0020", 0 }, { "BRCM2032", 0 }, { "HISI0031", 0 }, { }, }; MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); static struct platform_driver dw8250_platform_driver = { .driver = { .name = "dw-apb-uart", .pm = &dw8250_pm_ops, .of_match_table = dw8250_of_match, .acpi_match_table = ACPI_PTR(dw8250_acpi_match), }, .probe = dw8250_probe, .remove = dw8250_remove, }; module_platform_driver(dw8250_platform_driver); MODULE_AUTHOR("Jamie Iles"); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); MODULE_ALIAS("platform:dw-apb-uart");
Information contained on this website is for historical information purposes only and does not indicate or represent copyright ownership.
Created with Cregit http://github.com/cregit/cregit
Version 2.0-RC1