Contributors: 1
Author Tokens Token Proportion Commits Commit Proportion
Adam Aharon 196 100.00% 1 100.00%
Total 196 1 


/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_PSOC_CPU_PLL_REGS_H_
#define ASIC_REG_PSOC_CPU_PLL_REGS_H_

/*
 *****************************************
 *   PSOC_CPU_PLL (Prototype: PLL)
 *****************************************
 */

#define mmPSOC_CPU_PLL_NR                                            0xC70100

#define mmPSOC_CPU_PLL_NF                                            0xC70104

#define mmPSOC_CPU_PLL_OD                                            0xC70108

#define mmPSOC_CPU_PLL_NB                                            0xC7010C

#define mmPSOC_CPU_PLL_CFG                                           0xC70110

#define mmPSOC_CPU_PLL_LOSE_MASK                                     0xC70120

#define mmPSOC_CPU_PLL_LOCK_INTR                                     0xC70128

#define mmPSOC_CPU_PLL_LOCK_BYPASS                                   0xC7012C

#define mmPSOC_CPU_PLL_DATA_CHNG                                     0xC70130

#define mmPSOC_CPU_PLL_RST                                           0xC70134

#define mmPSOC_CPU_PLL_SLIP_WD_CNTR                                  0xC70150

#define mmPSOC_CPU_PLL_DIV_FACTOR_0                                  0xC70200

#define mmPSOC_CPU_PLL_DIV_FACTOR_1                                  0xC70204

#define mmPSOC_CPU_PLL_DIV_FACTOR_2                                  0xC70208

#define mmPSOC_CPU_PLL_DIV_FACTOR_3                                  0xC7020C

#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_0                              0xC70220

#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_1                              0xC70224

#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_2                              0xC70228

#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_3                              0xC7022C

#define mmPSOC_CPU_PLL_DIV_SEL_0                                     0xC70280

#define mmPSOC_CPU_PLL_DIV_SEL_1                                     0xC70284

#define mmPSOC_CPU_PLL_DIV_SEL_2                                     0xC70288

#define mmPSOC_CPU_PLL_DIV_SEL_3                                     0xC7028C

#define mmPSOC_CPU_PLL_DIV_EN_0                                      0xC702A0

#define mmPSOC_CPU_PLL_DIV_EN_1                                      0xC702A4

#define mmPSOC_CPU_PLL_DIV_EN_2                                      0xC702A8

#define mmPSOC_CPU_PLL_DIV_EN_3                                      0xC702AC

#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_0                             0xC702C0

#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_1                             0xC702C4

#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_2                             0xC702C8

#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_3                             0xC702CC

#define mmPSOC_CPU_PLL_CLK_GATER                                     0xC70300

#define mmPSOC_CPU_PLL_CLK_RLX_0                                     0xC70310

#define mmPSOC_CPU_PLL_CLK_RLX_1                                     0xC70314

#define mmPSOC_CPU_PLL_CLK_RLX_2                                     0xC70318

#define mmPSOC_CPU_PLL_CLK_RLX_3                                     0xC7031C

#define mmPSOC_CPU_PLL_REF_CNTR_PERIOD                               0xC70400

#define mmPSOC_CPU_PLL_REF_LOW_THRESHOLD                             0xC70410

#define mmPSOC_CPU_PLL_REF_HIGH_THRESHOLD                            0xC70420

#define mmPSOC_CPU_PLL_PLL_NOT_STABLE                                0xC70430

#define mmPSOC_CPU_PLL_FREQ_CALC_EN                                  0xC70440

#define mmPSOC_CPU_PLL_RLX_BITMAP_CFG                                0xC70500

#define mmPSOC_CPU_PLL_RLX_BITMAP_0                                  0xC70510

#define mmPSOC_CPU_PLL_RLX_BITMAP_1                                  0xC70514

#define mmPSOC_CPU_PLL_RLX_BITMAP_2                                  0xC70518

#define mmPSOC_CPU_PLL_RLX_BITMAP_3                                  0xC7051C

#endif /* ASIC_REG_PSOC_CPU_PLL_REGS_H_ */