| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Oded Gabbay | 193 | 100.00% | 1 | 100.00% |
| Total | 193 | 1 |
/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DMA_MACRO_MASKS_H_ #define ASIC_REG_DMA_MACRO_MASKS_H_ /* ***************************************** * DMA_MACRO (Prototype: DMA_MACRO) ***************************************** */ /* DMA_MACRO_LBW_RANGE_HIT_BLOCK */ #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF /* DMA_MACRO_LBW_RANGE_MASK */ #define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0 #define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF /* DMA_MACRO_LBW_RANGE_BASE */ #define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0 #define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF /* DMA_MACRO_HBW_RANGE_HIT_BLOCK */ #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF /* DMA_MACRO_HBW_RANGE_MASK_49_32 */ #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF /* DMA_MACRO_HBW_RANGE_MASK_31_0 */ #define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK 0xFFFFFFFF /* DMA_MACRO_HBW_RANGE_BASE_49_32 */ #define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK 0x3FFFF /* DMA_MACRO_HBW_RANGE_BASE_31_0 */ #define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT 0 #define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK 0xFFFFFFFF /* DMA_MACRO_WRITE_EN */ #define DMA_MACRO_WRITE_EN_R_SHIFT 0 #define DMA_MACRO_WRITE_EN_R_MASK 0x1 /* DMA_MACRO_WRITE_CREDIT */ #define DMA_MACRO_WRITE_CREDIT_R_SHIFT 0 #define DMA_MACRO_WRITE_CREDIT_R_MASK 0x3FF /* DMA_MACRO_READ_EN */ #define DMA_MACRO_READ_EN_R_SHIFT 0 #define DMA_MACRO_READ_EN_R_MASK 0x1 /* DMA_MACRO_READ_CREDIT */ #define DMA_MACRO_READ_CREDIT_R_SHIFT 0 #define DMA_MACRO_READ_CREDIT_R_MASK 0x3FF /* DMA_MACRO_SRAM_BUSY */ /* DMA_MACRO_RAZWI_LBW_WT_VLD */ #define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_LBW_WT_ID */ #define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK 0x7FFF /* DMA_MACRO_RAZWI_LBW_RD_VLD */ #define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_LBW_RD_ID */ #define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK 0x7FFF /* DMA_MACRO_RAZWI_HBW_WT_VLD */ #define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_HBW_WT_ID */ #define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK 0x1FFFFFFF /* DMA_MACRO_RAZWI_HBW_RD_VLD */ #define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK 0x1 /* DMA_MACRO_RAZWI_HBW_RD_ID */ #define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT 0 #define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK 0x1FFFFFFF #endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */
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