Author | Tokens | Token Proportion | Commits | Commit Proportion |
---|---|---|---|---|
Oded Gabbay | 420 | 100.00% | 1 | 100.00% |
Total | 420 | 1 |
/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_TPC0_NRTR_REGS_H_ #define ASIC_REG_TPC0_NRTR_REGS_H_ /* ***************************************** * TPC0_NRTR (Prototype: IF_NRTR) ***************************************** */ #define mmTPC0_NRTR_HBW_MAX_CRED 0xE00100 #define mmTPC0_NRTR_LBW_MAX_CRED 0xE00120 #define mmTPC0_NRTR_DBG_E_ARB 0xE00300 #define mmTPC0_NRTR_DBG_W_ARB 0xE00304 #define mmTPC0_NRTR_DBG_N_ARB 0xE00308 #define mmTPC0_NRTR_DBG_S_ARB 0xE0030C #define mmTPC0_NRTR_DBG_L_ARB 0xE00310 #define mmTPC0_NRTR_DBG_E_ARB_MAX 0xE00320 #define mmTPC0_NRTR_DBG_W_ARB_MAX 0xE00324 #define mmTPC0_NRTR_DBG_N_ARB_MAX 0xE00328 #define mmTPC0_NRTR_DBG_S_ARB_MAX 0xE0032C #define mmTPC0_NRTR_DBG_L_ARB_MAX 0xE00330 #define mmTPC0_NRTR_SPLIT_COEF_0 0xE00400 #define mmTPC0_NRTR_SPLIT_COEF_1 0xE00404 #define mmTPC0_NRTR_SPLIT_COEF_2 0xE00408 #define mmTPC0_NRTR_SPLIT_COEF_3 0xE0040C #define mmTPC0_NRTR_SPLIT_COEF_4 0xE00410 #define mmTPC0_NRTR_SPLIT_COEF_5 0xE00414 #define mmTPC0_NRTR_SPLIT_COEF_6 0xE00418 #define mmTPC0_NRTR_SPLIT_COEF_7 0xE0041C #define mmTPC0_NRTR_SPLIT_COEF_8 0xE00420 #define mmTPC0_NRTR_SPLIT_COEF_9 0xE00424 #define mmTPC0_NRTR_SPLIT_CFG 0xE00440 #define mmTPC0_NRTR_SPLIT_RD_SAT 0xE00444 #define mmTPC0_NRTR_SPLIT_RD_RST_TOKEN 0xE00448 #define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_0 0xE0044C #define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_1 0xE00450 #define mmTPC0_NRTR_SPLIT_WR_SAT 0xE00454 #define mmTPC0_NRTR_WPLIT_WR_TST_TOLEN 0xE00458 #define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_0 0xE0045C #define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_1 0xE00460 #define mmTPC0_NRTR_HBW_RANGE_HIT 0xE00470 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_0 0xE00480 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_1 0xE00484 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_2 0xE00488 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_3 0xE0048C #define mmTPC0_NRTR_HBW_RANGE_MASK_L_4 0xE00490 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_5 0xE00494 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_6 0xE00498 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_7 0xE0049C #define mmTPC0_NRTR_HBW_RANGE_MASK_H_0 0xE004A0 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_1 0xE004A4 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_2 0xE004A8 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_3 0xE004AC #define mmTPC0_NRTR_HBW_RANGE_MASK_H_4 0xE004B0 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_5 0xE004B4 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_6 0xE004B8 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_7 0xE004BC #define mmTPC0_NRTR_HBW_RANGE_BASE_L_0 0xE004C0 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_1 0xE004C4 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_2 0xE004C8 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_3 0xE004CC #define mmTPC0_NRTR_HBW_RANGE_BASE_L_4 0xE004D0 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_5 0xE004D4 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_6 0xE004D8 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_7 0xE004DC #define mmTPC0_NRTR_HBW_RANGE_BASE_H_0 0xE004E0 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_1 0xE004E4 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_2 0xE004E8 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_3 0xE004EC #define mmTPC0_NRTR_HBW_RANGE_BASE_H_4 0xE004F0 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_5 0xE004F4 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_6 0xE004F8 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_7 0xE004FC #define mmTPC0_NRTR_LBW_RANGE_HIT 0xE00500 #define mmTPC0_NRTR_LBW_RANGE_MASK_0 0xE00510 #define mmTPC0_NRTR_LBW_RANGE_MASK_1 0xE00514 #define mmTPC0_NRTR_LBW_RANGE_MASK_2 0xE00518 #define mmTPC0_NRTR_LBW_RANGE_MASK_3 0xE0051C #define mmTPC0_NRTR_LBW_RANGE_MASK_4 0xE00520 #define mmTPC0_NRTR_LBW_RANGE_MASK_5 0xE00524 #define mmTPC0_NRTR_LBW_RANGE_MASK_6 0xE00528 #define mmTPC0_NRTR_LBW_RANGE_MASK_7 0xE0052C #define mmTPC0_NRTR_LBW_RANGE_MASK_8 0xE00530 #define mmTPC0_NRTR_LBW_RANGE_MASK_9 0xE00534 #define mmTPC0_NRTR_LBW_RANGE_MASK_10 0xE00538 #define mmTPC0_NRTR_LBW_RANGE_MASK_11 0xE0053C #define mmTPC0_NRTR_LBW_RANGE_MASK_12 0xE00540 #define mmTPC0_NRTR_LBW_RANGE_MASK_13 0xE00544 #define mmTPC0_NRTR_LBW_RANGE_MASK_14 0xE00548 #define mmTPC0_NRTR_LBW_RANGE_MASK_15 0xE0054C #define mmTPC0_NRTR_LBW_RANGE_BASE_0 0xE00550 #define mmTPC0_NRTR_LBW_RANGE_BASE_1 0xE00554 #define mmTPC0_NRTR_LBW_RANGE_BASE_2 0xE00558 #define mmTPC0_NRTR_LBW_RANGE_BASE_3 0xE0055C #define mmTPC0_NRTR_LBW_RANGE_BASE_4 0xE00560 #define mmTPC0_NRTR_LBW_RANGE_BASE_5 0xE00564 #define mmTPC0_NRTR_LBW_RANGE_BASE_6 0xE00568 #define mmTPC0_NRTR_LBW_RANGE_BASE_7 0xE0056C #define mmTPC0_NRTR_LBW_RANGE_BASE_8 0xE00570 #define mmTPC0_NRTR_LBW_RANGE_BASE_9 0xE00574 #define mmTPC0_NRTR_LBW_RANGE_BASE_10 0xE00578 #define mmTPC0_NRTR_LBW_RANGE_BASE_11 0xE0057C #define mmTPC0_NRTR_LBW_RANGE_BASE_12 0xE00580 #define mmTPC0_NRTR_LBW_RANGE_BASE_13 0xE00584 #define mmTPC0_NRTR_LBW_RANGE_BASE_14 0xE00588 #define mmTPC0_NRTR_LBW_RANGE_BASE_15 0xE0058C #define mmTPC0_NRTR_RGLTR 0xE00590 #define mmTPC0_NRTR_RGLTR_WR_RESULT 0xE00594 #define mmTPC0_NRTR_RGLTR_RD_RESULT 0xE00598 #define mmTPC0_NRTR_SCRAMB_EN 0xE00600 #define mmTPC0_NRTR_NON_LIN_SCRAMB 0xE00604 #endif /* ASIC_REG_TPC0_NRTR_REGS_H_ */
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