Contributors: 3
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| mtk01761 |
178 |
93.68% |
1 |
33.33% |
| Miles Chen |
9 |
4.74% |
1 |
33.33% |
| Chen-Yu Tsai |
3 |
1.58% |
1 |
33.33% |
| Total |
190 |
|
3 |
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6779-clk.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
};
static int clk_mt6779_mfg_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt6779_mfg[] = {
{ .compatible = "mediatek,mt6779-mfgcfg", },
{}
};
static struct platform_driver clk_mt6779_mfg_drv = {
.probe = clk_mt6779_mfg_probe,
.driver = {
.name = "clk-mt6779-mfg",
.of_match_table = of_match_clk_mt6779_mfg,
},
};
module_platform_driver(clk_mt6779_mfg_drv);
MODULE_LICENSE("GPL");