| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Joonwoo Park | 12930 | 75.56% | 1 | 4.17% |
| Marijn Suijten | 1694 | 9.90% | 3 | 12.50% |
| Jeffrey Hugo | 1549 | 9.05% | 10 | 41.67% |
| Björn Andersson | 388 | 2.27% | 2 | 8.33% |
| Michael Srba | 272 | 1.59% | 1 | 4.17% |
| Angelo G. Del Regno | 230 | 1.34% | 4 | 16.67% |
| Stephen Boyd | 46 | 0.27% | 1 | 4.17% |
| Taniya Das | 2 | 0.01% | 1 | 4.17% |
| Marc Gonzalez | 1 | 0.01% | 1 | 4.17% |
| Total | 17112 | 24 |
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2016, The Linux Foundation. All rights reserved. */ #include <linux/kernel.h> #include <linux/bitops.h> #include <linux/err.h> #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> #include <dt-bindings/clock/qcom,gcc-msm8998.h> #include "common.h" #include "clk-regmap.h" #include "clk-alpha-pll.h" #include "clk-pll.h" #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" #include "gdsc.h" static struct pll_vco fabia_vco[] = { { 250000000, 2000000000, 0 }, { 125000000, 1000000000, 1 }, }; static struct clk_alpha_pll gpll0 = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_alpha_pll_fixed_fabia_ops, } }, }; static struct clk_alpha_pll_postdiv gpll0_out_even = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_even", .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll0_out_main = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_main", .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll0_out_odd = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_odd", .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll0_out_test = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_test", .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll gpll1 = { .offset = 0x1000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gpll1", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_alpha_pll_fixed_fabia_ops, } }, }; static struct clk_alpha_pll_postdiv gpll1_out_even = { .offset = 0x1000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll1_out_even", .parent_hws = (const struct clk_hw*[]) { &gpll1.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll1_out_main = { .offset = 0x1000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll1_out_main", .parent_hws = (const struct clk_hw*[]) { &gpll1.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll1_out_odd = { .offset = 0x1000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll1_out_odd", .parent_hws = (const struct clk_hw*[]) { &gpll1.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll1_out_test = { .offset = 0x1000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll1_out_test", .parent_hws = (const struct clk_hw*[]) { &gpll1.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll gpll2 = { .offset = 0x2000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gpll2", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_alpha_pll_fixed_fabia_ops, } }, }; static struct clk_alpha_pll_postdiv gpll2_out_even = { .offset = 0x2000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll2_out_even", .parent_hws = (const struct clk_hw*[]) { &gpll2.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll2_out_main = { .offset = 0x2000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll2_out_main", .parent_hws = (const struct clk_hw*[]) { &gpll2.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll2_out_odd = { .offset = 0x2000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll2_out_odd", .parent_hws = (const struct clk_hw*[]) { &gpll2.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll2_out_test = { .offset = 0x2000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll2_out_test", .parent_hws = (const struct clk_hw*[]) { &gpll2.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll gpll3 = { .offset = 0x3000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gpll3", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_alpha_pll_fixed_fabia_ops, } }, }; static struct clk_alpha_pll_postdiv gpll3_out_even = { .offset = 0x3000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll3_out_even", .parent_hws = (const struct clk_hw*[]) { &gpll3.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll3_out_main = { .offset = 0x3000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll3_out_main", .parent_hws = (const struct clk_hw*[]) { &gpll3.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll3_out_odd = { .offset = 0x3000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll3_out_odd", .parent_hws = (const struct clk_hw*[]) { &gpll3.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll3_out_test = { .offset = 0x3000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll3_out_test", .parent_hws = (const struct clk_hw*[]) { &gpll3.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll gpll4 = { .offset = 0x77000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gpll4", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_alpha_pll_fixed_fabia_ops, } }, }; static struct clk_alpha_pll_postdiv gpll4_out_even = { .offset = 0x77000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4_out_even", .parent_hws = (const struct clk_hw*[]) { &gpll4.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll4_out_main = { .offset = 0x77000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4_out_main", .parent_hws = (const struct clk_hw*[]) { &gpll4.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll4_out_odd = { .offset = 0x77000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4_out_odd", .parent_hws = (const struct clk_hw*[]) { &gpll4.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; static struct clk_alpha_pll_postdiv gpll4_out_test = { .offset = 0x77000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4_out_test", .parent_hws = (const struct clk_hw*[]) { &gpll4.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; enum { P_AUD_REF_CLK, P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL4_OUT_MAIN, P_PLL0_EARLY_DIV_CLK_SRC, P_SLEEP_CLK, P_XO, }; static const struct parent_map gcc_parent_map_0[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_0[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_1[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_1[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_2[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_SLEEP_CLK, 5 }, { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_2[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "sleep_clk" }, { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_3[] = { { P_XO, 0 }, { P_SLEEP_CLK, 5 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "xo" }, { .fw_name = "sleep_clk" }, { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_4[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL4_OUT_MAIN, 5 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_4[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll4_out_main.clkr.hw }, { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_5[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_AUD_REF_CLK, 2 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "xo" }, { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "aud_ref_clk" }, { .fw_name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), { } }; static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .cmd_rcgr = 0x19020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { F(960000, P_XO, 10, 1, 2), F(4800000, P_XO, 4, 0, 0), F(9600000, P_XO, 2, 0, 0), F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), F(19200000, P_XO, 1, 0, 0), F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), { } }; static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .cmd_rcgr = 0x1900c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .cmd_rcgr = 0x1b020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .cmd_rcgr = 0x1b00c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .cmd_rcgr = 0x1d020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .cmd_rcgr = 0x1d00c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .cmd_rcgr = 0x1f020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .cmd_rcgr = 0x1f00c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .cmd_rcgr = 0x21020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .cmd_rcgr = 0x2100c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .cmd_rcgr = 0x23020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .cmd_rcgr = 0x2300c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), F(19200000, P_XO, 1, 0, 0), F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), { } }; static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .cmd_rcgr = 0x1a00c, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .cmd_rcgr = 0x1c00c, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .cmd_rcgr = 0x1e00c, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .cmd_rcgr = 0x26020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .cmd_rcgr = 0x2600c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .cmd_rcgr = 0x28020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .cmd_rcgr = 0x2800c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .cmd_rcgr = 0x2a020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .cmd_rcgr = 0x2a00c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .cmd_rcgr = 0x2c020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .cmd_rcgr = 0x2c00c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .cmd_rcgr = 0x2e020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .cmd_rcgr = 0x2e00c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .cmd_rcgr = 0x30020, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_i2c_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .cmd_rcgr = 0x3000c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .cmd_rcgr = 0x2700c, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .cmd_rcgr = 0x2900c, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .cmd_rcgr = 0x2b00c, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart3_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gp1_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), { } }; static struct clk_rcg2 gp1_clk_src = { .cmd_rcgr = 0x64004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gp2_clk_src = { .cmd_rcgr = 0x65004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gp3_clk_src = { .cmd_rcgr = 0x66004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), { } }; static struct clk_rcg2 hmss_ahb_clk_src = { .cmd_rcgr = 0x48014, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_hmss_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_ahb_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { F(19200000, P_XO, 1, 0, 0), { } }; static struct clk_rcg2 hmss_rbcpr_clk_src = { .cmd_rcgr = 0x48044, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_hmss_rbcpr_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_rbcpr_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { F(1010526, P_XO, 1, 1, 19), { } }; static struct clk_rcg2 pcie_aux_clk_src = { .cmd_rcgr = 0x6c000, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_pcie_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_pdm2_clk_src[] = { F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), { } }; static struct clk_rcg2 pdm2_clk_src = { .cmd_rcgr = 0x33010, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_pdm2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { F(144000, P_XO, 16, 3, 25), F(400000, P_XO, 12, 1, 4), F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), { } }; static struct clk_rcg2 sdcc2_apps_clk_src = { .cmd_rcgr = 0x14010, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_4, .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_floor_ops, }, }; static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = { F(144000, P_XO, 16, 3, 25), F(400000, P_XO, 12, 1, 4), F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), { } }; static struct clk_rcg2 sdcc4_apps_clk_src = { .cmd_rcgr = 0x16010, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_sdcc4_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc4_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_floor_ops, }, }; static const struct freq_tbl ftbl_tsif_ref_clk_src[] = { F(105495, P_XO, 1, 1, 182), { } }; static struct clk_rcg2 tsif_ref_clk_src = { .cmd_rcgr = 0x36010, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_5, .freq_tbl = ftbl_tsif_ref_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), { } }; static struct clk_rcg2 ufs_axi_clk_src = { .cmd_rcgr = 0x75018, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_ufs_axi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_axi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), { } }; static struct clk_rcg2 ufs_unipro_core_clk_src = { .cmd_rcgr = 0x76028, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_ufs_unipro_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_unipro_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_usb30_master_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), { } }; static struct clk_rcg2 usb30_master_clk_src = { .cmd_rcgr = 0xf014, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_usb30_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 usb30_mock_utmi_clk_src = { .cmd_rcgr = 0xf028, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_hmss_rbcpr_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { F(1200000, P_XO, 16, 0, 0), { } }; static struct clk_rcg2 usb3_phy_aux_clk_src = { .cmd_rcgr = 0x5000c, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_usb3_phy_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; static struct clk_branch gcc_aggre1_noc_xo_clk = { .halt_reg = 0x8202c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x8202c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre1_noc_xo_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_aggre1_ufs_axi_clk = { .halt_reg = 0x82028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x82028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre1_ufs_axi_clk", .parent_hws = (const struct clk_hw *[]) { &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_aggre1_usb3_axi_clk = { .halt_reg = 0x82024, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x82024, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre1_usb3_axi_clk", .parent_hws = (const struct clk_hw *[]) { &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = { .halt_reg = 0x48090, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x48090, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_apss_qdss_tsctr_div2_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = { .halt_reg = 0x48094, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x48094, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_apss_qdss_tsctr_div8_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_bimc_hmss_axi_clk = { .halt_reg = 0x48004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_bimc_hmss_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_bimc_mss_q6_axi_clk = { .halt_reg = 0x4401c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4401c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_bimc_mss_q6_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mss_cfg_ahb_clk = { .halt_reg = 0x8a000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x8a000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_cfg_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mss_snoc_axi_clk = { .halt_reg = 0x8a03c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x8a03c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_snoc_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { .halt_reg = 0x8a004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x8a004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_mnoc_bimc_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_boot_rom_ahb_clk = { .halt_reg = 0x38004, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x38004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_boot_rom_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mmss_gpll0_clk = { .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_gpll0_clk", .parent_hws = (const struct clk_hw *[]) { &gpll0_out_main.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mss_gpll0_div_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_gpll0_div_clk_src", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_ahb_clk = { .halt_reg = 0x17004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .halt_reg = 0x19008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x19008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .halt_reg = 0x19004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x19004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .halt_reg = 0x1b008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1b008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .halt_reg = 0x1b004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1b004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .halt_reg = 0x1d008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1d008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .halt_reg = 0x1d004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1d004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .halt_reg = 0x1f008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1f008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .halt_reg = 0x1f004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1f004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { .halt_reg = 0x21008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x21008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup5_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { .halt_reg = 0x21004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x21004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup5_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { .halt_reg = 0x23008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x23008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup6_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .halt_reg = 0x23004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x23004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup6_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_sleep_clk = { .halt_reg = 0x17008, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_sleep_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_uart1_apps_clk = { .halt_reg = 0x1a004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1a004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart1_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_uart2_apps_clk = { .halt_reg = 0x1c004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1c004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart2_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_uart3_apps_clk = { .halt_reg = 0x1e004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1e004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart3_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_ahb_clk = { .halt_reg = 0x25004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { .halt_reg = 0x26008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x26008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { .halt_reg = 0x26004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x26004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { .halt_reg = 0x28008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x28008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { .halt_reg = 0x28004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x28004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { .halt_reg = 0x2a008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2a008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { .halt_reg = 0x2a004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2a004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { .halt_reg = 0x2c008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2c008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { .halt_reg = 0x2c004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2c004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { .halt_reg = 0x2e008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2e008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup5_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { .halt_reg = 0x2e004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2e004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup5_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { .halt_reg = 0x30008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x30008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup6_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { .halt_reg = 0x30004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x30004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_qup6_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_sleep_clk = { .halt_reg = 0x25008, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_sleep_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_uart1_apps_clk = { .halt_reg = 0x27004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x27004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart1_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_uart2_apps_clk = { .halt_reg = 0x29004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x29004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart2_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp2_uart3_apps_clk = { .halt_reg = 0x2b004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2b004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart3_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp2_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { .halt_reg = 0x5018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_axi_clk", .parent_hws = (const struct clk_hw *[]) { &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x64000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x64000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", .parent_hws = (const struct clk_hw *[]) { &gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gp2_clk = { .halt_reg = 0x65000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x65000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", .parent_hws = (const struct clk_hw *[]) { &gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gp3_clk = { .halt_reg = 0x66000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x66000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", .parent_hws = (const struct clk_hw *[]) { &gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_bimc_gfx_clk = { .halt_reg = 0x46040, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x46040, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_bimc_gfx_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_bimc_gfx_clk = { .halt_reg = 0x71010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x71010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_bimc_gfx_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { .halt_reg = 0x7100c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x7100c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_bimc_gfx_src_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_cfg_ahb_clk = { .halt_reg = 0x71004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x71004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_cfg_ahb_clk", .ops = &clk_branch2_ops, /* * The GPU IOMMU depends on this clock and hypervisor * will crash the SoC if this clock goes down, due to * secure contexts protection. */ .flags = CLK_IS_CRITICAL, }, }, }; static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .halt_reg = 0x71018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x71018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_snoc_dvm_gfx_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_hmss_ahb_clk = { .halt_reg = 0x48000, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_hmss_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &hmss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_hmss_at_clk = { .halt_reg = 0x48010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x48010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hmss_at_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_hmss_rbcpr_clk = { .halt_reg = 0x48008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x48008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hmss_rbcpr_clk", .parent_hws = (const struct clk_hw *[]) { &hmss_rbcpr_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_hmss_trig_clk = { .halt_reg = 0x4800c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4800c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hmss_trig_clk", .ops = &clk_branch2_ops, }, }, }; static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 hmss_gpll0_clk_src = { .cmd_rcgr = 0x4805c, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_hmss_gpll0_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "hmss_gpll0_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { .halt_reg = 0x9004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_noc_cfg_ahb_clk", .ops = &clk_branch2_ops, /* * Any access to mmss depends on this clock. * Gating this clock has been shown to crash the system * when mmssnoc_axi_rpm_clk is inited in rpmcc. */ .flags = CLK_IS_CRITICAL, }, }, }; static struct clk_branch gcc_mmss_qm_ahb_clk = { .halt_reg = 0x9030, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9030, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_qm_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mmss_qm_core_clk = { .halt_reg = 0x900c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x900c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_qm_core_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mmss_sys_noc_axi_clk = { .halt_reg = 0x9000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_sys_noc_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mss_at_clk = { .halt_reg = 0x8a00c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x8a00c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_at_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pcie_0_aux_clk = { .halt_reg = 0x6b014, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6b014, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", .parent_hws = (const struct clk_hw *[]) { &pcie_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { .halt_reg = 0x6b010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6b010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_cfg_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pcie_0_mstr_axi_clk = { .halt_reg = 0x6b00c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6b00c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_mstr_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x6b018, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x6b018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pcie_0_slv_axi_clk = { .halt_reg = 0x6b008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6b008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_slv_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pcie_phy_aux_clk = { .halt_reg = 0x6f004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6f004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_aux_clk", .parent_hws = (const struct clk_hw *[]) { &pcie_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x3300c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x3300c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", .parent_hws = (const struct clk_hw *[]) { &pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm_ahb_clk = { .halt_reg = 0x33004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x33004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm_xo4_clk = { .halt_reg = 0x33008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x33008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_xo4_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_prng_ahb_clk = { .halt_reg = 0x34004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_prng_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc2_ahb_clk = { .halt_reg = 0x14008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x14008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc2_apps_clk = { .halt_reg = 0x14004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x14004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", .parent_hws = (const struct clk_hw *[]) { &sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc4_ahb_clk = { .halt_reg = 0x16008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x16008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc4_apps_clk = { .halt_reg = 0x16004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x16004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk", .parent_hws = (const struct clk_hw *[]) { &sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_tsif_ahb_clk = { .halt_reg = 0x36004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x36004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_tsif_inactivity_timers_clk = { .halt_reg = 0x3600c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x3600c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_inactivity_timers_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_tsif_ref_clk = { .halt_reg = 0x36008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x36008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk", .parent_hws = (const struct clk_hw *[]) { &tsif_ref_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_ahb_clk = { .halt_reg = 0x7500c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x7500c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_axi_clk = { .halt_reg = 0x75008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x75008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_axi_clk", .parent_hws = (const struct clk_hw *[]) { &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_ice_core_clk = { .halt_reg = 0x7600c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x7600c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ice_core_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_aux_clk = { .halt_reg = 0x76040, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x76040, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_aux_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .halt_reg = 0x75014, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75014, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_0_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .halt_reg = 0x7605c, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x7605c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_1_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .halt_reg = 0x75010, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_symbol_0_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_unipro_core_clk = { .halt_reg = 0x76008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x76008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_unipro_core_clk", .parent_hws = (const struct clk_hw *[]) { &ufs_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb30_master_clk = { .halt_reg = 0xf008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xf008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_master_clk", .parent_hws = (const struct clk_hw *[]) { &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb30_mock_utmi_clk = { .halt_reg = 0xf010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xf010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mock_utmi_clk", .parent_hws = (const struct clk_hw *[]) { &usb30_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb30_sleep_clk = { .halt_reg = 0xf00c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xf00c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sleep_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb3_phy_aux_clk = { .halt_reg = 0x50000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x50000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_aux_clk", .parent_hws = (const struct clk_hw *[]) { &usb3_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb3_phy_pipe_clk = { .halt_reg = 0x50004, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x50004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_pipe_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { .halt_reg = 0x6a004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6a004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_phy_cfg_ahb2phy_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_hdmi_clkref_clk = { .halt_reg = 0x88000, .clkr = { .enable_reg = 0x88000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hdmi_clkref_clk", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_clkref_clk = { .halt_reg = 0x88004, .clkr = { .enable_reg = 0x88004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_clkref_clk", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb3_clkref_clk = { .halt_reg = 0x88008, .clkr = { .enable_reg = 0x88008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_clkref_clk", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pcie_clkref_clk = { .halt_reg = 0x8800c, .clkr = { .enable_reg = 0x8800c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_clkref_clk", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_rx1_usb2_clkref_clk = { .halt_reg = 0x88014, .clkr = { .enable_reg = 0x88014, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_rx1_usb2_clkref_clk", .parent_data = (const struct clk_parent_data []) { { .fw_name = "xo" }, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_im_sleep_clk = { .halt_reg = 0x4300c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4300c, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gcc_im_sleep_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch aggre2_snoc_north_axi_clk = { .halt_reg = 0x83010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x83010, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "aggre2_snoc_north_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch ssc_xo_clk = { .halt_reg = 0x63018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x63018, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "ssc_xo_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch ssc_cnoc_ahbs_clk = { .halt_reg = 0x6300c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6300c, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "ssc_cnoc_ahbs_clk", .ops = &clk_branch2_ops, }, }, }; static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .gds_hw_ctrl = 0x0, .pd = { .name = "pcie_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; static struct gdsc ufs_gdsc = { .gdscr = 0x75004, .gds_hw_ctrl = 0x0, .pd = { .name = "ufs_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; static struct gdsc usb_30_gdsc = { .gdscr = 0xf004, .gds_hw_ctrl = 0x0, .pd = { .name = "usb_30_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; static struct clk_regmap *gcc_msm8998_clocks[] = { [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr, [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr, [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr, [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr, [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr, [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr, [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr, [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr, [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, [GP1_CLK_SRC] = &gp1_clk_src.clkr, [GP2_CLK_SRC] = &gp2_clk_src.clkr, [GP3_CLK_SRC] = &gp3_clk_src.clkr, [GPLL0] = &gpll0.clkr, [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, [GPLL0_OUT_TEST] = &gpll0_out_test.clkr, [GPLL1] = &gpll1.clkr, [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr, [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr, [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr, [GPLL1_OUT_TEST] = &gpll1_out_test.clkr, [GPLL2] = &gpll2.clkr, [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr, [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr, [GPLL2_OUT_TEST] = &gpll2_out_test.clkr, [GPLL3] = &gpll3.clkr, [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr, [GPLL3_OUT_TEST] = &gpll3_out_test.clkr, [GPLL4] = &gpll4.clkr, [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr, [GPLL4_OUT_TEST] = &gpll4_out_test.clkr, [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr, [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, [SSC_XO] = &ssc_xo_clk.clkr, [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { [PCIE_0_GDSC] = &pcie_0_gdsc, [UFS_GDSC] = &ufs_gdsc, [USB_30_GDSC] = &usb_30_gdsc, }; static const struct qcom_reset_map gcc_msm8998_resets[] = { [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, [GCC_PCIE_0_BCR] = { 0x6b000 }, [GCC_PDM_BCR] = { 0x33000 }, [GCC_SDCC2_BCR] = { 0x14000 }, [GCC_SDCC4_BCR] = { 0x16000 }, [GCC_TSIF_BCR] = { 0x36000 }, [GCC_UFS_BCR] = { 0x75000 }, [GCC_USB_30_BCR] = { 0xf000 }, [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, [GCC_CONFIG_NOC_BCR] = { 0x5000 }, [GCC_AHB2PHY_EAST_BCR] = { 0x7000 }, [GCC_IMEM_BCR] = { 0x8000 }, [GCC_PIMEM_BCR] = { 0xa000 }, [GCC_MMSS_BCR] = { 0xb000 }, [GCC_QDSS_BCR] = { 0xc000 }, [GCC_WCSS_BCR] = { 0x11000 }, [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, [GCC_BLSP1_BCR] = { 0x17000 }, [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 }, [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 }, [GCC_BLSP2_BCR] = { 0x25000 }, [GCC_BLSP2_UART1_BCR] = { 0x27000 }, [GCC_BLSP2_UART2_BCR] = { 0x29000 }, [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, [GCC_SRAM_SENSOR_BCR] = { 0x2d000 }, [GCC_PRNG_BCR] = { 0x34000 }, [GCC_TSIF_0_RESET] = { 0x36024 }, [GCC_TSIF_1_RESET] = { 0x36028 }, [GCC_TCSR_BCR] = { 0x37000 }, [GCC_BOOT_ROM_BCR] = { 0x38000 }, [GCC_MSG_RAM_BCR] = { 0x39000 }, [GCC_TLMM_BCR] = { 0x3a000 }, [GCC_MPM_BCR] = { 0x3b000 }, [GCC_SEC_CTRL_BCR] = { 0x3d000 }, [GCC_SPMI_BCR] = { 0x3f000 }, [GCC_SPDM_BCR] = { 0x40000 }, [GCC_CE1_BCR] = { 0x41000 }, [GCC_BIMC_BCR] = { 0x44000 }, [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 }, [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 }, [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 }, [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 }, [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c }, [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, [GCC_APB2JTAG_BCR] = { 0x4c000 }, [GCC_RBCPR_CX_BCR] = { 0x4e000 }, [GCC_RBCPR_MX_BCR] = { 0x4f000 }, [GCC_USB3_PHY_BCR] = { 0x50020 }, [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, [GCC_SSC_BCR] = { 0x63000 }, [GCC_SSC_RESET] = { 0x63020 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, [GCC_PCIE_PHY_BCR] = { 0x6f000 }, [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c }, [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 }, [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 }, [GCC_GPU_BCR] = { 0x71000 }, [GCC_SPSS_BCR] = { 0x72000 }, [GCC_OBT_ODT_BCR] = { 0x73000 }, [GCC_MSS_RESTART] = { 0x79000 }, [GCC_VS_BCR] = { 0x7a000 }, [GCC_MSS_VS_RESET] = { 0x7a100 }, [GCC_GPU_VS_RESET] = { 0x7a104 }, [GCC_APC0_VS_RESET] = { 0x7a108 }, [GCC_APC1_VS_RESET] = { 0x7a10c }, [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 }, [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 }, [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 }, [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 }, [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 }, [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 }, [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, [GCC_DCC_BCR] = { 0x84000 }, [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 }, [GCC_IPA_BCR] = { 0x89000 }, [GCC_GLM_BCR] = { 0x8b000 }, [GCC_SKL_BCR] = { 0x8c000 }, [GCC_MSMPU_BCR] = { 0x8d000 }, }; static const struct regmap_config gcc_msm8998_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x8f000, .fast_io = true, }; static const struct qcom_cc_desc gcc_msm8998_desc = { .config = &gcc_msm8998_regmap_config, .clks = gcc_msm8998_clocks, .num_clks = ARRAY_SIZE(gcc_msm8998_clocks), .resets = gcc_msm8998_resets, .num_resets = ARRAY_SIZE(gcc_msm8998_resets), .gdscs = gcc_msm8998_gdscs, .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs), }; static int gcc_msm8998_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; regmap = qcom_cc_map(pdev, &gcc_msm8998_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); /* * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be * turned off by hardware during certain apps low power modes. */ ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); if (ret) return ret; return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); } static const struct of_device_id gcc_msm8998_match_table[] = { { .compatible = "qcom,gcc-msm8998" }, { } }; MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table); static struct platform_driver gcc_msm8998_driver = { .probe = gcc_msm8998_probe, .driver = { .name = "gcc-msm8998", .of_match_table = gcc_msm8998_match_table, }, }; static int __init gcc_msm8998_init(void) { return platform_driver_register(&gcc_msm8998_driver); } core_initcall(gcc_msm8998_init); static void __exit gcc_msm8998_exit(void) { platform_driver_unregister(&gcc_msm8998_driver); } module_exit(gcc_msm8998_exit); MODULE_DESCRIPTION("QCOM GCC msm8998 Driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:gcc-msm8998");
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