Author | Tokens | Token Proportion | Commits | Commit Proportion |
---|---|---|---|---|
Giovanni Cabiddu | 499 | 58.09% | 2 | 40.00% |
Marco Chiappero | 216 | 25.15% | 2 | 40.00% |
Wojciech Ziemba | 144 | 16.76% | 1 | 20.00% |
Total | 859 | 5 |
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) /* Copyright(c) 2020 Intel Corporation */ #include <linux/iopoll.h> #include "adf_accel_devices.h" #include "adf_common_drv.h" #include "adf_gen4_hw_data.h" static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size) { return BUILD_RING_BASE_ADDR(addr, size); } static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) { return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); } static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, u32 value) { WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); } static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) { return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); } static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, u32 value) { WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); } static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) { return READ_CSR_E_STAT(csr_base_addr, bank); } static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring, u32 value) { WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value); } static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring, dma_addr_t addr) { WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); } static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value) { WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); } static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank) { WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); } static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value) { WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); } static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank, u32 value) { WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); } static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank, u32 value) { WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value); } static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank, u32 value) { WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value); } void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops) { csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr; csr_ops->read_csr_ring_head = read_csr_ring_head; csr_ops->write_csr_ring_head = write_csr_ring_head; csr_ops->read_csr_ring_tail = read_csr_ring_tail; csr_ops->write_csr_ring_tail = write_csr_ring_tail; csr_ops->read_csr_e_stat = read_csr_e_stat; csr_ops->write_csr_ring_config = write_csr_ring_config; csr_ops->write_csr_ring_base = write_csr_ring_base; csr_ops->write_csr_int_flag = write_csr_int_flag; csr_ops->write_csr_int_srcsel = write_csr_int_srcsel; csr_ops->write_csr_int_col_en = write_csr_int_col_en; csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl; csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col; csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en; } EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops); static inline void adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper, u32 *lower) { *lower = lower_32_bits(value); *upper = upper_32_bits(value); } void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev) { void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE; u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE; u32 ssm_wdt_pke_high = 0; u32 ssm_wdt_pke_low = 0; u32 ssm_wdt_high = 0; u32 ssm_wdt_low = 0; /* Convert 64bit WDT timer value into 32bit values for * mmio write to 32bit CSRs. */ adf_gen4_unpack_ssm_wdtimer(timer_val, &ssm_wdt_high, &ssm_wdt_low); adf_gen4_unpack_ssm_wdtimer(timer_val_pke, &ssm_wdt_pke_high, &ssm_wdt_pke_low); /* Enable WDT for sym and dc */ ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low); ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high); /* Enable WDT for pke */ ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low); ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high); } EXPORT_SYMBOL_GPL(adf_gen4_set_ssm_wdtimer); int adf_pfvf_comms_disabled(struct adf_accel_dev *accel_dev) { return 0; } EXPORT_SYMBOL_GPL(adf_pfvf_comms_disabled); static int reset_ring_pair(void __iomem *csr, u32 bank_number) { u32 status; int ret; /* Write rpresetctl register BIT(0) as 1 * Since rpresetctl registers have no RW fields, no need to preserve * values for other bits. Just write directly. */ ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number), ADF_WQM_CSR_RPRESETCTL_RESET); /* Read rpresetsts register and wait for rp reset to complete */ ret = read_poll_timeout(ADF_CSR_RD, status, status & ADF_WQM_CSR_RPRESETSTS_STATUS, ADF_RPRESET_POLL_DELAY_US, ADF_RPRESET_POLL_TIMEOUT_US, true, csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); if (!ret) { /* When rp reset is done, clear rpresetsts */ ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number), ADF_WQM_CSR_RPRESETSTS_STATUS); } return ret; } int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number) { struct adf_hw_device_data *hw_data = accel_dev->hw_device; u32 etr_bar_id = hw_data->get_etr_bar_id(hw_data); void __iomem *csr; int ret; if (bank_number >= hw_data->num_banks) return -EINVAL; dev_dbg(&GET_DEV(accel_dev), "ring pair reset for bank:%d\n", bank_number); csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr; ret = reset_ring_pair(csr, bank_number); if (ret) dev_err(&GET_DEV(accel_dev), "ring pair reset failed (timeout)\n"); else dev_dbg(&GET_DEV(accel_dev), "ring pair reset successful\n"); return ret; } EXPORT_SYMBOL_GPL(adf_gen4_ring_pair_reset);
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