| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Oded Gabbay | 842 | 100.00% | 1 | 100.00% |
| Total | 842 | 1 |
/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_PSOC_ETR_MASKS_H_ #define ASIC_REG_PSOC_ETR_MASKS_H_ /* ***************************************** * PSOC_ETR * (Prototype: ETR) ***************************************** */ /* PSOC_ETR_RSZ */ #define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0 #define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF /* PSOC_ETR_STS */ #define PSOC_ETR_STS_FULL_SHIFT 0 #define PSOC_ETR_STS_FULL_MASK 0x1 #define PSOC_ETR_STS_TRIGGERED_SHIFT 1 #define PSOC_ETR_STS_TRIGGERED_MASK 0x2 #define PSOC_ETR_STS_TMCREADY_SHIFT 2 #define PSOC_ETR_STS_TMCREADY_MASK 0x4 #define PSOC_ETR_STS_FTEMPTY_SHIFT 3 #define PSOC_ETR_STS_FTEMPTY_MASK 0x8 #define PSOC_ETR_STS_EMPTY_SHIFT 4 #define PSOC_ETR_STS_EMPTY_MASK 0x10 #define PSOC_ETR_STS_MEMERR_SHIFT 5 #define PSOC_ETR_STS_MEMERR_MASK 0x20 /* PSOC_ETR_RRD */ #define PSOC_ETR_RRD_RRD_SHIFT 0 #define PSOC_ETR_RRD_RRD_MASK 0xFFFFFFFF /* PSOC_ETR_RRP */ #define PSOC_ETR_RRP_RRP_SHIFT 0 #define PSOC_ETR_RRP_RRP_MASK 0xFFFFFFFF /* PSOC_ETR_RWP */ #define PSOC_ETR_RWP_RWP_SHIFT 0 #define PSOC_ETR_RWP_RWP_MASK 0xFFFFFFFF /* PSOC_ETR_TRG */ #define PSOC_ETR_TRG_TRG_SHIFT 0 #define PSOC_ETR_TRG_TRG_MASK 0xFFFFFFFF /* PSOC_ETR_CTL */ #define PSOC_ETR_CTL_TRACECAPTEN_SHIFT 0 #define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1 /* PSOC_ETR_RWD */ #define PSOC_ETR_RWD_RWD_SHIFT 0 #define PSOC_ETR_RWD_RWD_MASK 0xFFFFFFFF /* PSOC_ETR_MODE */ #define PSOC_ETR_MODE_MODE_SHIFT 0 #define PSOC_ETR_MODE_MODE_MASK 0x3 /* PSOC_ETR_LBUFLEVEL */ #define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT 0 #define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK 0x7FFFFFFF /* PSOC_ETR_CBUFLEVEL */ #define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT 0 #define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK 0x7FFFFFFF /* PSOC_ETR_BUFWM */ #define PSOC_ETR_BUFWM_BUFWM_SHIFT 0 #define PSOC_ETR_BUFWM_BUFWM_MASK 0x3FFFFFFF /* PSOC_ETR_RRPHI */ #define PSOC_ETR_RRPHI_RRPHI_SHIFT 0 #define PSOC_ETR_RRPHI_RRPHI_MASK 0xFF /* PSOC_ETR_RWPHI */ #define PSOC_ETR_RWPHI_RWPHI_SHIFT 0 #define PSOC_ETR_RWPHI_RWPHI_MASK 0xFF /* PSOC_ETR_AXICTL */ #define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT 0 #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 #define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT 2 #define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK 0x4 #define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT 3 #define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK 0x8 #define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT 4 #define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK 0x10 #define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT 5 #define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK 0x20 #define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT 7 #define PSOC_ETR_AXICTL_SCATTERGATHERMODE_MASK 0x80 #define PSOC_ETR_AXICTL_WRBURSTLEN_SHIFT 8 #define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 /* PSOC_ETR_DBALO */ #define PSOC_ETR_DBALO_BUFADDRLO_SHIFT 0 #define PSOC_ETR_DBALO_BUFADDRLO_MASK 0xFFFFFFFF /* PSOC_ETR_DBAHI */ #define PSOC_ETR_DBAHI_BUFADDRHI_SHIFT 0 #define PSOC_ETR_DBAHI_BUFADDRHI_MASK 0xFF /* PSOC_ETR_FFSR */ #define PSOC_ETR_FFSR_FLINPROG_SHIFT 0 #define PSOC_ETR_FFSR_FLINPROG_MASK 0x1 #define PSOC_ETR_FFSR_FTSTOPPED_SHIFT 1 #define PSOC_ETR_FFSR_FTSTOPPED_MASK 0x2 /* PSOC_ETR_FFCR */ #define PSOC_ETR_FFCR_ENFT_SHIFT 0 #define PSOC_ETR_FFCR_ENFT_MASK 0x1 #define PSOC_ETR_FFCR_ENTI_SHIFT 1 #define PSOC_ETR_FFCR_ENTI_MASK 0x2 #define PSOC_ETR_FFCR_FONFLIN_SHIFT 4 #define PSOC_ETR_FFCR_FONFLIN_MASK 0x10 #define PSOC_ETR_FFCR_FONTRIGEVT_SHIFT 5 #define PSOC_ETR_FFCR_FONTRIGEVT_MASK 0x20 #define PSOC_ETR_FFCR_FLUSHMAN_SHIFT 6 #define PSOC_ETR_FFCR_FLUSHMAN_MASK 0x40 #define PSOC_ETR_FFCR_TRIGONTRIGIN_SHIFT 8 #define PSOC_ETR_FFCR_TRIGONTRIGIN_MASK 0x100 #define PSOC_ETR_FFCR_TRIGONTRIGEVT_SHIFT 9 #define PSOC_ETR_FFCR_TRIGONTRIGEVT_MASK 0x200 #define PSOC_ETR_FFCR_TRIGONFL_SHIFT 10 #define PSOC_ETR_FFCR_TRIGONFL_MASK 0x400 #define PSOC_ETR_FFCR_STOPONFL_SHIFT 12 #define PSOC_ETR_FFCR_STOPONFL_MASK 0x1000 #define PSOC_ETR_FFCR_STOPONTRIGEVT_SHIFT 13 #define PSOC_ETR_FFCR_STOPONTRIGEVT_MASK 0x2000 /* PSOC_ETR_PSCR */ #define PSOC_ETR_PSCR_PSCOUNT_SHIFT 0 #define PSOC_ETR_PSCR_PSCOUNT_MASK 0x1F /* PSOC_ETR_ITMISCOP0 */ #define PSOC_ETR_ITMISCOP0_ACQCOMP_SHIFT 0 #define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK 0x1 #define PSOC_ETR_ITMISCOP0_FULL_SHIFT 1 #define PSOC_ETR_ITMISCOP0_FULL_MASK 0x2 /* PSOC_ETR_ITTRFLIN */ #define PSOC_ETR_ITTRFLIN_TRIGIN_SHIFT 0 #define PSOC_ETR_ITTRFLIN_TRIGIN_MASK 0x1 #define PSOC_ETR_ITTRFLIN_FLUSHIN_SHIFT 1 #define PSOC_ETR_ITTRFLIN_FLUSHIN_MASK 0x2 /* PSOC_ETR_ITATBDATA0 */ #define PSOC_ETR_ITATBDATA0_ATDATASBIT0_SHIFT 0 #define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK 0x1 #define PSOC_ETR_ITATBDATA0_ATDATASBIT7_SHIFT 1 #define PSOC_ETR_ITATBDATA0_ATDATASBIT7_MASK 0x2 #define PSOC_ETR_ITATBDATA0_ATDATASBIT15_SHIFT 2 #define PSOC_ETR_ITATBDATA0_ATDATASBIT15_MASK 0x4 #define PSOC_ETR_ITATBDATA0_ATDATASBIT23_SHIFT 3 #define PSOC_ETR_ITATBDATA0_ATDATASBIT23_MASK 0x8 #define PSOC_ETR_ITATBDATA0_ATDATASBIT31_SHIFT 4 #define PSOC_ETR_ITATBDATA0_ATDATASBIT31_MASK 0x10 #define PSOC_ETR_ITATBDATA0_ATDATASBIT39_SHIFT 5 #define PSOC_ETR_ITATBDATA0_ATDATASBIT39_MASK 0x20 #define PSOC_ETR_ITATBDATA0_ATDATASBIT47_SHIFT 6 #define PSOC_ETR_ITATBDATA0_ATDATASBIT47_MASK 0x40 #define PSOC_ETR_ITATBDATA0_ATDATASBIT55_SHIFT 7 #define PSOC_ETR_ITATBDATA0_ATDATASBIT55_MASK 0x80 #define PSOC_ETR_ITATBDATA0_ATDATASBIT63_SHIFT 8 #define PSOC_ETR_ITATBDATA0_ATDATASBIT63_MASK 0x100 /* PSOC_ETR_ITATBCTR2 */ #define PSOC_ETR_ITATBCTR2_ATREADYS_SHIFT 0 #define PSOC_ETR_ITATBCTR2_ATREADYS_MASK 0x1 #define PSOC_ETR_ITATBCTR2_AFVALIDS_SHIFT 1 #define PSOC_ETR_ITATBCTR2_AFVALIDS_MASK 0x2 #define PSOC_ETR_ITATBCTR2_SYNCREQS_SHIFT 2 #define PSOC_ETR_ITATBCTR2_SYNCREQS_MASK 0x4 /* PSOC_ETR_ITATBCTR1 */ #define PSOC_ETR_ITATBCTR1_ATIDS_SHIFT 0 #define PSOC_ETR_ITATBCTR1_ATIDS_MASK 0x7F /* PSOC_ETR_ITATBCTR0 */ #define PSOC_ETR_ITATBCTR0_ATVALIDS_SHIFT 0 #define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK 0x1 #define PSOC_ETR_ITATBCTR0_AFREADYS_SHIFT 1 #define PSOC_ETR_ITATBCTR0_AFREADYS_MASK 0x2 #define PSOC_ETR_ITATBCTR0_ATBYTESS_SHIFT 8 #define PSOC_ETR_ITATBCTR0_ATBYTESS_MASK 0x700 /* PSOC_ETR_ITCTRL */ #define PSOC_ETR_ITCTRL_INTEGRATION_MODE_SHIFT 0 #define PSOC_ETR_ITCTRL_INTEGRATION_MODE_MASK 0x1 /* PSOC_ETR_CLAIMSET */ #define PSOC_ETR_CLAIMSET_CLAIMSET_SHIFT 0 #define PSOC_ETR_CLAIMSET_CLAIMSET_MASK 0xF /* PSOC_ETR_CLAIMCLR */ #define PSOC_ETR_CLAIMCLR_CLAIMCLR_SHIFT 0 #define PSOC_ETR_CLAIMCLR_CLAIMCLR_MASK 0xF /* PSOC_ETR_LAR */ #define PSOC_ETR_LAR_ACCESS_W_SHIFT 0 #define PSOC_ETR_LAR_ACCESS_W_MASK 0xFFFFFFFF /* PSOC_ETR_LSR */ #define PSOC_ETR_LSR_LOCKEXIST_SHIFT 0 #define PSOC_ETR_LSR_LOCKEXIST_MASK 0x1 #define PSOC_ETR_LSR_LOCKGRANT_SHIFT 1 #define PSOC_ETR_LSR_LOCKGRANT_MASK 0x2 #define PSOC_ETR_LSR_LOCKTYPE_SHIFT 2 #define PSOC_ETR_LSR_LOCKTYPE_MASK 0x4 /* PSOC_ETR_AUTHSTATUS */ #define PSOC_ETR_AUTHSTATUS_NSID_SHIFT 0 #define PSOC_ETR_AUTHSTATUS_NSID_MASK 0x3 #define PSOC_ETR_AUTHSTATUS_NSNID_SHIFT 2 #define PSOC_ETR_AUTHSTATUS_NSNID_MASK 0xC #define PSOC_ETR_AUTHSTATUS_SID_SHIFT 4 #define PSOC_ETR_AUTHSTATUS_SID_MASK 0x30 #define PSOC_ETR_AUTHSTATUS_SNID_SHIFT 6 #define PSOC_ETR_AUTHSTATUS_SNID_MASK 0xC0 /* PSOC_ETR_DEVID */ #define PSOC_ETR_DEVID_ATBINPORTCOUNT_SHIFT 0 #define PSOC_ETR_DEVID_ATBINPORTCOUNT_MASK 0x1F #define PSOC_ETR_DEVID_CLKSCHEME_SHIFT 5 #define PSOC_ETR_DEVID_CLKSCHEME_MASK 0x20 #define PSOC_ETR_DEVID_CONFIGTYPE_SHIFT 6 #define PSOC_ETR_DEVID_CONFIGTYPE_MASK 0xC0 #define PSOC_ETR_DEVID_MEMWIDTH_SHIFT 8 #define PSOC_ETR_DEVID_MEMWIDTH_MASK 0x700 #define PSOC_ETR_DEVID_WBUF_DEPTH_SHIFT 11 #define PSOC_ETR_DEVID_WBUF_DEPTH_MASK 0x3800 /* PSOC_ETR_DEVTYPE */ #define PSOC_ETR_DEVTYPE_MAJOR_TYPE_SHIFT 0 #define PSOC_ETR_DEVTYPE_MAJOR_TYPE_MASK 0xF #define PSOC_ETR_DEVTYPE_SUB_TYPE_SHIFT 4 #define PSOC_ETR_DEVTYPE_SUB_TYPE_MASK 0xF0 /* PSOC_ETR_PERIPHID4 */ #define PSOC_ETR_PERIPHID4_JEP106_CONT_SHIFT 0 #define PSOC_ETR_PERIPHID4_JEP106_CONT_MASK 0xF #define PSOC_ETR_PERIPHID4_FOURKB_COUNT_SHIFT 4 #define PSOC_ETR_PERIPHID4_FOURKB_COUNT_MASK 0xF0 /* PSOC_ETR_PERIPHID5 */ #define PSOC_ETR_PERIPHID5_PERIPHID5_SHIFT 0 #define PSOC_ETR_PERIPHID5_PERIPHID5_MASK 0xFFFFFFFF /* PSOC_ETR_PERIPHID6 */ #define PSOC_ETR_PERIPHID6_PERIPHID6_SHIFT 0 #define PSOC_ETR_PERIPHID6_PERIPHID6_MASK 0xFFFFFFFF /* PSOC_ETR_PERIPHID7 */ #define PSOC_ETR_PERIPHID7_PERIPHID7_SHIFT 0 #define PSOC_ETR_PERIPHID7_PERIPHID7_MASK 0xFFFFFFFF /* PSOC_ETR_PERIPHID0 */ #define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_SHIFT 0 #define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_MASK 0xFF /* PSOC_ETR_PERIPHID1 */ #define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_SHIFT 0 #define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_MASK 0xF #define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_SHIFT 4 #define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_MASK 0xF0 /* PSOC_ETR_PERIPHID2 */ #define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_SHIFT 0 #define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_MASK 0x7 #define PSOC_ETR_PERIPHID2_JEDEC_SHIFT 3 #define PSOC_ETR_PERIPHID2_JEDEC_MASK 0x8 #define PSOC_ETR_PERIPHID2_REVISION_SHIFT 4 #define PSOC_ETR_PERIPHID2_REVISION_MASK 0xF0 /* PSOC_ETR_PERIPHID3 */ #define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_SHIFT 0 #define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_MASK 0xF #define PSOC_ETR_PERIPHID3_REVAND_SHIFT 4 #define PSOC_ETR_PERIPHID3_REVAND_MASK 0xF0 /* PSOC_ETR_COMPID0 */ #define PSOC_ETR_COMPID0_PREAMBLE_SHIFT 0 #define PSOC_ETR_COMPID0_PREAMBLE_MASK 0xFF /* PSOC_ETR_COMPID1 */ #define PSOC_ETR_COMPID1_PREAMBLE_SHIFT 0 #define PSOC_ETR_COMPID1_PREAMBLE_MASK 0xF #define PSOC_ETR_COMPID1_F_CLASS_SHIFT 4 #define PSOC_ETR_COMPID1_F_CLASS_MASK 0xF0 /* PSOC_ETR_COMPID2 */ #define PSOC_ETR_COMPID2_PREAMBLE_SHIFT 0 #define PSOC_ETR_COMPID2_PREAMBLE_MASK 0xFF /* PSOC_ETR_COMPID3 */ #define PSOC_ETR_COMPID3_PREAMBLE_SHIFT 0 #define PSOC_ETR_COMPID3_PREAMBLE_MASK 0xFF #endif /* ASIC_REG_PSOC_ETR_MASKS_H_ */
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