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Total 2640 1 


/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_

/*
 *****************************************
 *   PSOC_GLOBAL_CONF
 *   (Prototype: GLOBAL_CONF)
 *****************************************
 */

#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0x4C4B000

#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0x4C4B004

#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0x4C4B008

#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0x4C4B00C

#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0x4C4B020

#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0x4C4B024

#define mmPSOC_GLOBAL_CONF_BTM_FSM 0x4C4B028

#define mmPSOC_GLOBAL_CONF_BTL_ROM_DELAY 0x4C4B02C

#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0x4C4B030

#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0x4C4B034

#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0x4C4B038

#define mmPSOC_GLOBAL_CONF_QSPI_SPI 0x4C4B03C

#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0x4C4B040

#define mmPSOC_GLOBAL_CONF_PRSTN 0x4C4B044

#define mmPSOC_GLOBAL_CONF_PCIE_EN 0x4C4B048

#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0x4C4B04C

#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0x4C4B050

#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0x4C4B054

#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0x4C4B058

#define mmPSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST 0x4C4B05C

#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0x4C4B060

#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0x4C4B064

#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0x4C4B068

#define mmPSOC_GLOBAL_CONF_ANY_RST 0x4C4B06C

#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0x4C4B070

#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0x4C4B074

#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0x4C4B078

#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0x4C4B07C

#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0x4C4B080

#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0x4C4B084

#define mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT 0x4C4B088

#define mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO 0x4C4B08C

#define mmPSOC_GLOBAL_CONF_BTL_PROT 0x4C4B090

#define mmPSOC_GLOBAL_CONF_BTL_ADDR_EXT 0x4C4B094

#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0x4C4B098

#define mmPSOC_GLOBAL_CONF_RESET_DELAYS 0x4C4B09C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0x4C4B100

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0x4C4B104

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0x4C4B108

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0x4C4B10C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0x4C4B110

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0x4C4B114

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0x4C4B118

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0x4C4B11C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0x4C4B120

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0x4C4B124

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0x4C4B128

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0x4C4B12C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0x4C4B130

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0x4C4B134

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0x4C4B138

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0x4C4B13C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0x4C4B140

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0x4C4B144

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0x4C4B148

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0x4C4B14C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0x4C4B150

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0x4C4B154

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0x4C4B158

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0x4C4B15C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0x4C4B160

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0x4C4B164

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0x4C4B168

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0x4C4B16C

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0x4C4B170

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0x4C4B174

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0x4C4B178

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0x4C4B17C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0x4C4B200

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0x4C4B204

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0x4C4B208

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0x4C4B20C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0x4C4B210

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0x4C4B214

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0x4C4B218

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0x4C4B21C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0x4C4B220

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0x4C4B224

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0x4C4B228

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0x4C4B22C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0x4C4B230

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0x4C4B234

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0x4C4B238

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0x4C4B23C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0x4C4B240

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0x4C4B244

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0x4C4B248

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0x4C4B24C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0x4C4B250

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0x4C4B254

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0x4C4B258

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0x4C4B25C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0x4C4B260

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0x4C4B264

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0x4C4B268

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0x4C4B26C

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0x4C4B270

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0x4C4B274

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0x4C4B278

#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0x4C4B27C

#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0x4C4B300

#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0x4C4B304

#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0x4C4B308

#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0x4C4B30C

#define mmPSOC_GLOBAL_CONF_I2C_SLV 0x4C4B310

#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0x4C4B314

#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0x4C4B320

#define mmPSOC_GLOBAL_CONF_SMB_ALERT_CTRL 0x4C4B324

#define mmPSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE 0x4C4B328

#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR 0x4C4B32C

#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL 0x4C4B330

#define mmPSOC_GLOBAL_CONF_TRACE_AXPROT 0x4C4B334

#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0x4C4B338

#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0x4C4B33C

#define mmPSOC_GLOBAL_CONF_BTL_STS 0x4C4B340

#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0x4C4B350

#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0x4C4B354

#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0x4C4B358

#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0x4C4B35C

#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0x4C4B360

#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR 0x4C4B368

#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR_MASK 0x4C4B36C

#define mmPSOC_GLOBAL_CONF_DBG_APB_CTRL 0x4C4B370

#define mmPSOC_GLOBAL_CONF_SPI_DMA_BAUDR 0x4C4B374

#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWPROT 0x4C4B378

#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWUSER 0x4C4B37C

#define mmPSOC_GLOBAL_CONF_SPI_DMA_CTRL 0x4C4B380

#define mmPSOC_GLOBAL_CONF_SPI_DMA_STATUS 0x4C4B384

#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L 0x4C4B388

#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H 0x4C4B38C

#define mmPSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL 0x4C4B3A0

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_CTRL 0x4C4B3B0

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L 0x4C4B3B4

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H 0x4C4B3B8

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L 0x4C4B3BC

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H 0x4C4B3C0

#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L 0x4C4B3C4

#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H 0x4C4B3CC

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS 0x4C4B3D0

#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS 0x4C4B3D4

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR 0x4C4B3D8

#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR 0x4C4B3DC

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK 0x4C4B3E0

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE 0x4C4B3E4

#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR 0x4C4B3E8

#define mmPSOC_GLOBAL_CONF_MSTR_IF 0x4C4B3F0

#define mmPSOC_GLOBAL_CONF_TARGETID 0x4C4B400

#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_0 0x4C4B404

#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_1 0x4C4B408

#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_0 0x4C4B40C

#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_1 0x4C4B410

#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0x4C4B420

#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L 0x4C4B430

#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H 0x4C4B434

#define mmPSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS 0x4C4B438

#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0x4C4B44C

#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0x4C4B450

#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0x4C4B454

#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0x4C4B458

#define mmPSOC_GLOBAL_CONF_MASK_REQ 0x4C4B45C

#define mmPSOC_GLOBAL_CONF_BSAC_CTRL 0x4C4B4C0

#define mmPSOC_GLOBAL_CONF_BSAC_ADDR 0x4C4B4C4

#define mmPSOC_GLOBAL_CONF_BSAC_DATA 0x4C4B4C8

#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_CTRL 0x4C4B4CC

#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_DATA 0x4C4B4D0

#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_MASK 0x4C4B4D4

#define mmPSOC_GLOBAL_CONF_BTL_IMG 0x4C4B4E0

#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0x4C4B4E4

#define mmPSOC_GLOBAL_CONF_WD_MASK 0x4C4B4E8

#define mmPSOC_GLOBAL_CONF_RST_SRC 0x4C4B4F0

#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0x4C4B4F4

#define mmPSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL 0x4C4B4F8

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0x4C4B500

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0x4C4B504

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0x4C4B508

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0x4C4B50C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0x4C4B510

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0x4C4B514

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0x4C4B518

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0x4C4B51C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0x4C4B520

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0x4C4B524

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0x4C4B528

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0x4C4B52C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0x4C4B530

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0x4C4B534

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0x4C4B538

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0x4C4B53C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0x4C4B540

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0x4C4B544

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0x4C4B548

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0x4C4B54C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0x4C4B550

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0x4C4B554

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0x4C4B558

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0x4C4B55C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0x4C4B560

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0x4C4B564

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0x4C4B568

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0x4C4B56C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0x4C4B570

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0x4C4B574

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0x4C4B578

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0x4C4B57C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0x4C4B580

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0x4C4B584

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0x4C4B588

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0x4C4B58C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0x4C4B590

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0x4C4B594

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0x4C4B598

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0x4C4B59C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0x4C4B5A0

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0x4C4B5A4

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0x4C4B5A8

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0x4C4B5AC

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0x4C4B5B0

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0x4C4B5B4

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0x4C4B5B8

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0x4C4B5BC

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0x4C4B5C0

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0x4C4B5C4

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0x4C4B5C8

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0x4C4B5CC

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0x4C4B5D0

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0x4C4B5D4

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0x4C4B5D8

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0x4C4B5DC

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0x4C4B5E0

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0x4C4B5E4

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0x4C4B5E8

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0x4C4B5EC

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0x4C4B5F0

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0x4C4B5F4

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0x4C4B5F8

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0x4C4B5FC

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0x4C4B600

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0x4C4B604

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0x4C4B608

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0x4C4B60C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0x4C4B610

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0x4C4B614

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0x4C4B618

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0x4C4B61C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0x4C4B620

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0x4C4B624

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0x4C4B628

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0x4C4B62C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0x4C4B630

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0x4C4B634

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0x4C4B638

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0x4C4B63C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0x4C4B640

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0x4C4B644

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0x4C4B648

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0x4C4B64C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0x4C4B650

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0x4C4B654

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0x4C4B658

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0x4C4B65C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0x4C4B660

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0x4C4B664

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_90 0x4C4B668

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_91 0x4C4B66C

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_92 0x4C4B670

#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_93 0x4C4B674

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0x4C4B690

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0x4C4B694

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0x4C4B698

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0x4C4B69C

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0x4C4B6A0

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0x4C4B6A4

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0x4C4B6A8

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0x4C4B6AC

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0x4C4B6B0

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0x4C4B6B4

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0x4C4B6B8

#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0x4C4B6BC

#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0x4C4B710

#define mmPSOC_GLOBAL_CONF_TPC_ISO 0x4C4B760

#define mmPSOC_GLOBAL_CONF_VDEC_ISO 0x4C4B764

#define mmPSOC_GLOBAL_CONF_NIC_ISO 0x4C4B768

#define mmPSOC_GLOBAL_CONF_MME_ISO 0x4C4B76C

#define mmPSOC_GLOBAL_CONF_EDMA_ISO 0x4C4B770

#define mmPSOC_GLOBAL_CONF_HBM_ISO 0x4C4B774

#define mmPSOC_GLOBAL_CONF_XBAR_EDGE_ISO 0x4C4B778

#define mmPSOC_GLOBAL_CONF_HIF_HMMU_ISO 0x4C4B77C

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_0 0x4C4B780

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_1 0x4C4B784

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_0 0x4C4B788

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_1 0x4C4B78C

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_0 0x4C4B790

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_1 0x4C4B794

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_0 0x4C4B798

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_1 0x4C4B79C

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_0 0x4C4B7A0

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_1 0x4C4B7A4

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_0 0x4C4B7A8

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_1 0x4C4B7AC

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_0 0x4C4B7B0

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_1 0x4C4B7B4

#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_STATUS 0x4C4B7B8

#define mmPSOC_GLOBAL_CONF_ASIF_CORE_CFG 0x4C4B7C0

#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT 0x4C4B7C4

#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR 0x4C4B7C8

#define mmPSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG 0x4C4B7CC

#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_0 0x4C4B7D0

#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_1 0x4C4B7D4

#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_0 0x4C4B7D8

#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_1 0x4C4B7DC

#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_0 0x4C4B7E0

#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_1 0x4C4B7E4

#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_0 0x4C4B7E8

#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_1 0x4C4B7EC

#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_0 0x4C4B7F0

#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_1 0x4C4B7F4

#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_0 0x4C4B7F8

#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_1 0x4C4B7FC

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0x4C4B800

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0x4C4B804

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0x4C4B808

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0x4C4B80C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0x4C4B810

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0x4C4B814

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0x4C4B818

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0x4C4B81C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0x4C4B820

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0x4C4B824

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0x4C4B828

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0x4C4B82C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0x4C4B830

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0x4C4B834

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0x4C4B838

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0x4C4B83C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0x4C4B840

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0x4C4B844

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0x4C4B848

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0x4C4B84C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0x4C4B850

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0x4C4B854

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0x4C4B858

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0x4C4B85C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0x4C4B860

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0x4C4B864

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0x4C4B868

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0x4C4B86C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0x4C4B870

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0x4C4B874

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0x4C4B878

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0x4C4B87C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0x4C4B880

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0x4C4B884

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0x4C4B888

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0x4C4B88C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0x4C4B890

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0x4C4B894

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0x4C4B898

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0x4C4B89C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0x4C4B8A0

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0x4C4B8A4

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0x4C4B8A8

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0x4C4B8AC

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0x4C4B8B0

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0x4C4B8B4

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0x4C4B8B8

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0x4C4B8BC

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0x4C4B8C0

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0x4C4B8C4

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0x4C4B8C8

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0x4C4B8CC

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0x4C4B8D0

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0x4C4B8D4

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0x4C4B8D8

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0x4C4B8DC

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0x4C4B8E0

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0x4C4B8E4

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0x4C4B8E8

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0x4C4B8EC

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0x4C4B8F0

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0x4C4B8F4

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0x4C4B8F8

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0x4C4B8FC

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0x4C4B900

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0x4C4B904

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0x4C4B908

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0x4C4B90C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0x4C4B910

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0x4C4B914

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0x4C4B918

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0x4C4B91C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0x4C4B920

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0x4C4B924

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0x4C4B928

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0x4C4B92C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0x4C4B930

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0x4C4B934

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0x4C4B938

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0x4C4B93C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0x4C4B940

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0x4C4B944

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0x4C4B948

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0x4C4B94C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0x4C4B950

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0x4C4B954

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0x4C4B958

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0x4C4B95C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0x4C4B960

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0x4C4B964

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0x4C4B968

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0x4C4B96C

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0x4C4B970

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0x4C4B974

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0x4C4B978

#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0x4C4B97C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0x4C4B980

#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0x4C4B984

#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0x4C4B988

#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0x4C4B98C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0x4C4B990

#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0x4C4B994

#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0x4C4B998

#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0x4C4B99C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0x4C4B9A0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0x4C4B9A4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0x4C4B9A8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0x4C4B9AC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0x4C4B9B0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0x4C4B9B4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0x4C4B9B8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0x4C4B9BC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0x4C4B9C0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0x4C4B9C4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0x4C4B9C8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0x4C4B9CC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0x4C4B9D0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0x4C4B9D4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0x4C4B9D8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0x4C4B9DC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0x4C4B9E0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0x4C4B9E4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0x4C4B9E8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0x4C4B9EC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0x4C4B9F0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0x4C4B9F4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0x4C4B9F8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0x4C4B9FC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0x4C4BA00

#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0x4C4BA04

#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0x4C4BA08

#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0x4C4BA0C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0x4C4BA10

#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0x4C4BA14

#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0x4C4BA18

#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0x4C4BA1C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0x4C4BA20

#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0x4C4BA24

#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0x4C4BA28

#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0x4C4BA2C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0x4C4BA30

#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0x4C4BA34

#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0x4C4BA38

#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0x4C4BA3C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0x4C4BA40

#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0x4C4BA44

#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0x4C4BA48

#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0x4C4BA4C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0x4C4BA50

#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0x4C4BA54

#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0x4C4BA58

#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0x4C4BA5C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0x4C4BA60

#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0x4C4BA64

#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0x4C4BA68

#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0x4C4BA6C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0x4C4BA70

#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0x4C4BA74

#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0x4C4BA78

#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0x4C4BA7C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0x4C4BA80

#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0x4C4BA84

#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0x4C4BA88

#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0x4C4BA8C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0x4C4BA90

#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0x4C4BA94

#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0x4C4BA98

#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0x4C4BA9C

#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0x4C4BAA0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0x4C4BAA4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0x4C4BAA8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0x4C4BAAC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0x4C4BAB0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0x4C4BAB4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0x4C4BAB8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0x4C4BABC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0x4C4BAC0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0x4C4BAC4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0x4C4BAC8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0x4C4BACC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0x4C4BAD0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0x4C4BAD4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0x4C4BAD8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0x4C4BADC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0x4C4BAE0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0x4C4BAE4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0x4C4BAE8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0x4C4BAEC

#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0x4C4BAF0

#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0x4C4BAF4

#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0x4C4BAF8

#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0x4C4BAFC

#define mmPSOC_GLOBAL_CONF_SMI_ACCESS_EN 0x4C4BB00

#define mmPSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN 0x4C4BB38

#define mmPSOC_GLOBAL_CONF_SCRAM_PERM_SEL 0x4C4BB3C

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_0 0x4C4BB40

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_1 0x4C4BB44

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_2 0x4C4BB48

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_3 0x4C4BB4C

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_4 0x4C4BB50

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_5 0x4C4BB54

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_6 0x4C4BB58

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_7 0x4C4BB5C

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_8 0x4C4BB60

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_9 0x4C4BB64

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_10 0x4C4BB68

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_11 0x4C4BB6C

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_12 0x4C4BB70

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_13 0x4C4BB74

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_14 0x4C4BB78

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_15 0x4C4BB7C

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_16 0x4C4BB80

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_17 0x4C4BB84

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_18 0x4C4BB88

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_19 0x4C4BB8C

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_20 0x4C4BB90

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_21 0x4C4BB94

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_22 0x4C4BB98

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_23 0x4C4BB9C

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_24 0x4C4BBA0

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_25 0x4C4BBA4

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_26 0x4C4BBA8

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_27 0x4C4BBAC

#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_28 0x4C4BBB0

#define mmPSOC_GLOBAL_CONF_CORE_MODE 0x4C4BBB4

#define mmPSOC_GLOBAL_CONF_EXTMEM_ID_LOC 0x4C4BBB8

#define mmPSOC_GLOBAL_CONF_LBW_USER_CTRL 0x4C4BBC0

#define mmPSOC_GLOBAL_CONF_ADC_STM_ID 0x4C4BBFC

#define mmPSOC_GLOBAL_CONF_ADC_0 0x4C4BC00

#define mmPSOC_GLOBAL_CONF_ADC_1 0x4C4BC04

#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_0 0x4C4BC10

#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_1 0x4C4BC14

#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_0 0x4C4BC20

#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_1 0x4C4BC24

#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_0 0x4C4BC30

#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_1 0x4C4BC34

#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_0 0x4C4BC40

#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_1 0x4C4BC44

#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_0 0x4C4BC50

#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_1 0x4C4BC54

#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_0 0x4C4BC60

#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_1 0x4C4BC64

#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_0 0x4C4BC70

#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_1 0x4C4BC74

#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_0 0x4C4BC80

#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_1 0x4C4BC84

#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_0 0x4C4BC90

#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_1 0x4C4BC94

#define mmPSOC_GLOBAL_CONF_ADC_PID_SEL 0x4C4BC98

#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_0 0x4C4BCA0

#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_1 0x4C4BCA4

#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_0 0x4C4BCA8

#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_1 0x4C4BCAC

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_0 0x4C4BCC0

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_1 0x4C4BCC4

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_2 0x4C4BCC8

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_3 0x4C4BCCC

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_4 0x4C4BCD0

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_5 0x4C4BCD4

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_6 0x4C4BCD8

#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_7 0x4C4BCDC

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_0 0x4C4BCE0

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_1 0x4C4BCE4

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_2 0x4C4BCE8

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_3 0x4C4BCEC

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_4 0x4C4BCF0

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_5 0x4C4BCF4

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_6 0x4C4BCF8

#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_7 0x4C4BCFC

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_0 0x4C4BD00

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_1 0x4C4BD04

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_2 0x4C4BD08

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_3 0x4C4BD0C

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_4 0x4C4BD10

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_5 0x4C4BD14

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_6 0x4C4BD18

#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_7 0x4C4BD1C

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_CTRL 0x4C4BD24

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L 0x4C4BD28

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H 0x4C4BD2C

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L 0x4C4BD30

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H 0x4C4BD34

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L 0x4C4BD38

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H 0x4C4BD3C

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L 0x4C4BD40

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H 0x4C4BD44

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L 0x4C4BD48

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H 0x4C4BD4C

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L 0x4C4BD50

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H 0x4C4BD54

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L 0x4C4BD58

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H 0x4C4BD5C

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L 0x4C4BD60

#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H 0x4C4BD64

#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL 0x4C4BD80

#define mmPSOC_GLOBAL_CONF_RST_OUT_CTRL 0x4C4BD84

#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL 0x4C4BD90

#define mmPSOC_GLOBAL_CONF_MEM_CPY_STATUS 0x4C4BD94

#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H 0x4C4BD98

#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L 0x4C4BD9C

#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H 0x4C4BDA0

#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L 0x4C4BDA4

#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL2 0x4C4BDA8

#define mmPSOC_GLOBAL_CONF_MEM_CPY_CONST 0x4C4BDAC

#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H 0x4C4BDB0

#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L 0x4C4BDB4

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_CFG 0x4C4BDC0

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 0x4C4BDC4

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 0x4C4BDC8

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 0x4C4BDCC

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 0x4C4BDD0

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 0x4C4BDD4

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 0x4C4BDD8

#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD 0x4C4BDE0

#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN 0x4C4BDE4

#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD 0x4C4BDE8

#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN 0x4C4BDEC

#define mmPSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 0x4C4BDF0

#define mmPSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 0x4C4BDF4

#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR 0x4C4BDF8

#define mmPSOC_GLOBAL_CONF_MEM_CPY_PROT 0x4C4BE08

#define mmPSOC_GLOBAL_CONF_ISOLATE_INPUTS 0x4C4BE10

#define mmPSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL 0x4C4BE14

#define mmPSOC_GLOBAL_CONF_ARC_JT_SEL 0x4C4BE28

#define mmPSOC_GLOBAL_CONF_PLL_DUMP_CRTL 0x4C4BE2C

#define mmPSOC_GLOBAL_CONF_MEM_CPY_AXUSER 0x4C4BE30

#define mmPSOC_GLOBAL_CONF_BTL_AXUSER 0x4C4BE34

#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 0x4C4BE38

#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 0x4C4BE40

#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 0x4C4BE44

#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 0x4C4BE48

#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_CTRL 0x4C4BE4C

#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT 0x4C4BE50

#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_INTR 0x4C4BE54

#define mmPSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK 0x4C4BE58

#define mmPSOC_GLOBAL_CONF_ECO_INTR_CAUSE 0x4C4BE60

#define mmPSOC_GLOBAL_CONF_ECO_INTR_CLEAR 0x4C4BE64

#define mmPSOC_GLOBAL_CONF_ECO_INTR_MASK 0x4C4BE68

#define mmPSOC_GLOBAL_CONF_DFT_APB_CONTROL 0x4C4BE70

#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */