Contributors: 1
Author Tokens Token Proportion Commits Commit Proportion
Dmitry Eremin-Solenikov 232 100.00% 2 100.00%
Total 232 2 


/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_

/* Only for QMP V3 PHY - TX registers */
#define QSERDES_V3_TX_BIST_MODE_LANENO			0x000
#define QSERDES_V3_TX_CLKBUF_ENABLE			0x008
#define QSERDES_V3_TX_TX_EMP_POST1_LVL			0x00c
#define QSERDES_V3_TX_TX_DRV_LVL			0x01c
#define QSERDES_V3_TX_RESET_TSYNC_EN			0x024
#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN		0x028
#define QSERDES_V3_TX_TX_BAND				0x02c
#define QSERDES_V3_TX_SLEW_CNTL				0x030
#define QSERDES_V3_TX_INTERFACE_SELECT			0x034
#define QSERDES_V3_TX_RES_CODE_LANE_TX			0x03c
#define QSERDES_V3_TX_RES_CODE_LANE_RX			0x040
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX		0x044
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX		0x048
#define QSERDES_V3_TX_DEBUG_BUS_SEL			0x058
#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN		0x05c
#define QSERDES_V3_TX_HIGHZ_DRVR_EN			0x060
#define QSERDES_V3_TX_TX_POL_INV			0x064
#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN	0x068
#define QSERDES_V3_TX_LANE_MODE_1			0x08c
#define QSERDES_V3_TX_LANE_MODE_2			0x090
#define QSERDES_V3_TX_LANE_MODE_3			0x094
#define QSERDES_V3_TX_RCV_DETECT_LVL_2			0x0a4
#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN			0x0c0
#define QSERDES_V3_TX_TX_INTERFACE_MODE			0x0c4
#define QSERDES_V3_TX_VMODE_CTRL1			0x0f0

/* Only for QMP V3 PHY - RX registers */
#define QSERDES_V3_RX_UCDR_FO_GAIN			0x008
#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF			0x00c
#define QSERDES_V3_RX_UCDR_SO_GAIN			0x014
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF		0x024
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER		0x028
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN			0x02c
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN		0x030
#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040
#define QSERDES_V3_RX_UCDR_PI_CONTROLS			0x044
#define QSERDES_V3_RX_RX_TERM_BW			0x07c
#define QSERDES_V3_RX_VGA_CAL_CNTRL1			0x0bc
#define QSERDES_V3_RX_VGA_CAL_CNTRL2			0x0c0
#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB			0x0c8
#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB			0x0cc
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1		0x0d0
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2		0x0d4
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3		0x0d8
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4		0x0dc
#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x0f8
#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x0fc
#define QSERDES_V3_RX_SIGDET_ENABLES			0x100
#define QSERDES_V3_RX_SIGDET_CNTRL			0x104
#define QSERDES_V3_RX_SIGDET_LVL			0x108
#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL		0x10c
#define QSERDES_V3_RX_RX_BAND				0x110
#define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c
#define QSERDES_V3_RX_RX_MODE_00			0x164
#define QSERDES_V3_RX_RX_MODE_01			0x168

#endif