Contributors: 23
Author Tokens Token Proportion Commits Commit Proportion
Nicholas Kazlauskas 187 35.08% 8 21.62%
Yongqiang Sun 63 11.82% 2 5.41%
Josip Pavic 53 9.94% 1 2.70%
Alvin lee 47 8.82% 5 13.51%
Harry Wentland 40 7.50% 1 2.70%
rodrigosiqueira 20 3.75% 1 2.70%
Wyatt Wood 16 3.00% 1 2.70%
Ashley Thomas 13 2.44% 1 2.70%
Max Tseng 12 2.25% 1 2.70%
Eric Yang 11 2.06% 2 5.41%
Mario Limonciello 9 1.69% 1 2.70%
Qingqing Zhuo 8 1.50% 1 2.70%
Leo (Hanghong) Ma 8 1.50% 1 2.70%
Jinze Xu 8 1.50% 1 2.70%
Samson Tam 7 1.31% 1 2.70%
Bhawanpreet Lakha 7 1.31% 2 5.41%
Aurabindo Pillai 7 1.31% 1 2.70%
Felipe Clark 6 1.13% 1 2.70%
Stylon Wang 4 0.75% 1 2.70%
Dillon Varone 3 0.56% 1 2.70%
Tony Cheng 2 0.38% 1 2.70%
Jerry (Fangzhi) Zuo 1 0.19% 1 2.70%
Anthony Koo 1 0.19% 1 2.70%
Total 533 37 


/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef _DMUB_DC_SRV_H_
#define _DMUB_DC_SRV_H_

#include "dm_services_types.h"
#include "dmub/dmub_srv.h"

struct dmub_srv;
struct dc;
struct pipe_ctx;
struct dc_crtc_timing_adjust;
struct dc_crtc_timing;
struct dc_state;
struct dc_surface_update;

struct dc_reg_helper_state {
	bool gather_in_progress;
	uint32_t same_addr_count;
	bool should_burst_write;
	union dmub_rb_cmd cmd_data;
	unsigned int reg_seq_count;
};

struct dc_dmub_srv {
	struct dmub_srv *dmub;
	struct dc_reg_helper_state reg_helper_offload;

	struct dc_context *ctx;
	void *dm;

	int32_t idle_exit_counter;
	bool idle_allowed;
	bool needs_idle_wake;
};

void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);

bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);

bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
		unsigned int count,
		union dmub_rb_cmd *cmd_list);

bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
		enum dm_dmub_wait_type wait_type,
		union dmub_rb_cmd *cmd_list);

bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);

bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type);

bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
				    unsigned int stream_mask);

bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);

bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);

void dc_dmub_trace_event_control(struct dc *dc, bool enable);

void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max);

void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);

void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv);
void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);
void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);

bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *dmub_oca);

void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);
void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);

void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx);
bool dc_dmub_check_min_version(struct dmub_srv *srv);

void dc_dmub_srv_enable_dpia_trace(const struct dc *dc);
void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index);

bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait);

void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle);

void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState);

/**
 * dc_wake_and_execute_dmub_cmd() - Wrapper for DMUB command execution.
 *
 * Refer to dc_wake_and_execute_dmub_cmd_list() for usage and limitations,
 * This function is a convenience wrapper for a single command execution.
 *
 * @ctx: DC context
 * @cmd: The command to send/receive
 * @wait_type: The wait behavior for the execution
 *
 * Return: true on command submission success, false otherwise
 */
bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,
				  enum dm_dmub_wait_type wait_type);

/**
 * dc_wake_and_execute_dmub_cmd_list() - Wrapper for DMUB command list execution.
 *
 * If the DMCUB hardware was asleep then it wakes the DMUB before
 * executing the command and attempts to re-enter if the command
 * submission was successful.
 *
 * This should be the preferred command submission interface provided
 * the DC lock is acquired.
 *
 * Entry/exit out of idle power optimizations would need to be
 * manually performed otherwise through dc_allow_idle_optimizations().
 *
 * @ctx: DC context
 * @count: Number of commands to send/receive
 * @cmd: Array of commands to send
 * @wait_type: The wait behavior for the execution
 *
 * Return: true on command submission success, false otherwise
 */
bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,
				       union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);

/**
 * dc_wake_and_execute_gpint()
 *
 * @ctx: DC context
 * @command_code: The command ID to send to DMCUB
 * @param: The parameter to message DMCUB
 * @response: Optional response out value - may be NULL.
 * @wait_type: The wait behavior for the execution
 */
bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
			       uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type);

#endif /* _DMUB_DC_SRV_H_ */