/* SPDX-License-Identifier: GPL-2.0 * * mt8186-audsys-clkid.h -- Mediatek 8186 audsys clock id definition * * Copyright (c) 2022 MediaTek Inc. * Author: Jiaxin Yu <jiaxin.yu@mediatek.com> */ #ifndef _MT8186_AUDSYS_CLKID_H_ #define _MT8186_AUDSYS_CLKID_H_ enum{ CLK_AUD_AFE, CLK_AUD_22M, CLK_AUD_24M, CLK_AUD_APLL2_TUNER, CLK_AUD_APLL_TUNER, CLK_AUD_TDM, CLK_AUD_ADC, CLK_AUD_DAC, CLK_AUD_DAC_PREDIS, CLK_AUD_TML, CLK_AUD_NLE, CLK_AUD_I2S1_BCLK, CLK_AUD_I2S2_BCLK, CLK_AUD_I2S3_BCLK, CLK_AUD_I2S4_BCLK, CLK_AUD_CONNSYS_I2S_ASRC, CLK_AUD_GENERAL1_ASRC, CLK_AUD_GENERAL2_ASRC, CLK_AUD_DAC_HIRES, CLK_AUD_ADC_HIRES, CLK_AUD_ADC_HIRES_TML, CLK_AUD_ADDA6_ADC, CLK_AUD_ADDA6_ADC_HIRES, CLK_AUD_3RD_DAC, CLK_AUD_3RD_DAC_PREDIS, CLK_AUD_3RD_DAC_TML, CLK_AUD_3RD_DAC_HIRES, CLK_AUD_ETDM_IN1_BCLK, CLK_AUD_ETDM_OUT1_BCLK, CLK_AUD_NR_CLK, }; #endif