| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Konrad Dybcio | 21454 | 99.97% | 1 | 25.00% |
| Luo Jie | 3 | 0.01% | 1 | 25.00% |
| Martin Botka | 2 | 0.01% | 1 | 25.00% |
| Julia Lawall | 1 | 0.00% | 1 | 25.00% |
| Total | 21460 | 4 |
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> */ #include <linux/kernel.h> #include <linux/err.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "common.h" #include "gdsc.h" #include "reset.h" enum { P_BI_TCXO, P_GPLL0_OUT_AUX2, P_GPLL0_OUT_EARLY, P_GPLL3_OUT_EARLY, P_GPLL4_OUT_MAIN, P_GPLL5_OUT_MAIN, P_GPLL6_OUT_EARLY, P_GPLL6_OUT_MAIN, P_GPLL7_OUT_MAIN, P_GPLL8_OUT_EARLY, P_GPLL8_OUT_MAIN, P_GPLL9_OUT_MAIN, P_SLEEP_CLK, }; static struct clk_alpha_pll gpll0_out_early = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_out_early", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_fixed_factor gpll0_out_aux2 = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll0_out_aux2", .parent_hws = (const struct clk_hw*[]){ &gpll0_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor gpll0_out_main = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll0_out_main", .parent_hws = (const struct clk_hw*[]){ &gpll0_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, }; static struct clk_alpha_pll gpll3_out_early = { .offset = 0x3000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gpll3_out_early", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_alpha_pll gpll4_out_main = { .offset = 0x4000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gpll4_out_main", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_alpha_pll gpll5_out_main = { .offset = 0x5000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gpll5_out_main", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_alpha_pll gpll6_out_early = { .offset = 0x6000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(6), .hw.init = &(struct clk_init_data){ .name = "gpll6_out_early", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_fixed_factor gpll6_out_main = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll6_out_main", .parent_hws = (const struct clk_hw*[]){ &gpll6_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, }; static struct clk_alpha_pll gpll7_out_early = { .offset = 0x7000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gpll7_out_early", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_fixed_factor gpll7_out_main = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll7_out_main", .parent_hws = (const struct clk_hw*[]){ &gpll7_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, }; static struct clk_alpha_pll gpll8_out_early = { .offset = 0x8000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "gpll8_out_early", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_fixed_factor gpll8_out_main = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll8_out_main", .parent_hws = (const struct clk_hw*[]){ &gpll8_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, }; static struct clk_alpha_pll gpll9_out_early = { .offset = 0x9000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x79000, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gpll9_out_early", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, }, }; static struct clk_fixed_factor gpll9_out_main = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll9_out_main", .parent_hws = (const struct clk_hw*[]){ &gpll9_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, }; static const struct parent_map gcc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL0_OUT_AUX2, 2 }, }; static const struct clk_parent_data gcc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll0_out_aux2.hw }, }; static const struct parent_map gcc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL0_OUT_AUX2, 2 }, { P_GPLL6_OUT_MAIN, 4 }, }; static const struct clk_parent_data gcc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll0_out_aux2.hw }, { .hw = &gpll6_out_main.hw }, }; static const struct parent_map gcc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL0_OUT_AUX2, 2 }, { P_SLEEP_CLK, 5 }, }; static const struct clk_parent_data gcc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll0_out_aux2.hw }, { .fw_name = "sleep_clk" }, }; static const struct parent_map gcc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL5_OUT_MAIN, 3 }, { P_GPLL4_OUT_MAIN, 5 }, }; static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll5_out_main.clkr.hw }, { .hw = &gpll4_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL9_OUT_MAIN, 2 }, }; static const struct clk_parent_data gcc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll9_out_main.hw }, }; static const struct parent_map gcc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, }; static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, }; static const struct parent_map gcc_parent_map_6[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL4_OUT_MAIN, 5 }, }; static const struct clk_parent_data gcc_parent_data_6[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll4_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_SLEEP_CLK, 5 }, }; static const struct clk_parent_data gcc_parent_data_7[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .fw_name = "sleep_clk" }, }; static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL9_OUT_MAIN, 2 }, { P_GPLL6_OUT_EARLY, 3 }, { P_GPLL8_OUT_MAIN, 4 }, { P_GPLL4_OUT_MAIN, 5 }, { P_GPLL3_OUT_EARLY, 6 }, }; static const struct clk_parent_data gcc_parent_data_8[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll9_out_main.hw }, { .hw = &gpll6_out_early.clkr.hw }, { .hw = &gpll8_out_main.hw }, { .hw = &gpll4_out_main.clkr.hw }, { .hw = &gpll3_out_early.clkr.hw }, }; static const struct parent_map gcc_parent_map_9[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL8_OUT_MAIN, 4 }, }; static const struct clk_parent_data gcc_parent_data_9[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll8_out_main.hw }, }; static const struct parent_map gcc_parent_map_10[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL9_OUT_MAIN, 2 }, { P_GPLL6_OUT_EARLY, 3 }, { P_GPLL8_OUT_MAIN, 4 }, { P_GPLL3_OUT_EARLY, 6 }, }; static const struct clk_parent_data gcc_parent_data_10[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll9_out_main.hw }, { .hw = &gpll6_out_early.clkr.hw }, { .hw = &gpll8_out_main.hw }, { .hw = &gpll3_out_early.clkr.hw }, }; static const struct parent_map gcc_parent_map_11[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL8_OUT_EARLY, 4 }, { P_GPLL4_OUT_MAIN, 5 }, }; static const struct clk_parent_data gcc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll8_out_early.clkr.hw }, { .hw = &gpll4_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_12[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL6_OUT_EARLY, 3 }, { P_GPLL8_OUT_EARLY, 4 }, }; static const struct clk_parent_data gcc_parent_data_12[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll6_out_early.clkr.hw }, { .hw = &gpll8_out_early.clkr.hw }, }; static const struct parent_map gcc_parent_map_13[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_EARLY, 1 }, { P_GPLL0_OUT_AUX2, 2 }, { P_GPLL7_OUT_MAIN, 3 }, { P_GPLL4_OUT_MAIN, 5 }, }; static const struct clk_parent_data gcc_parent_data_13[] = { { .fw_name = "bi_tcxo" }, { .hw = &gpll0_out_early.clkr.hw }, { .hw = &gpll0_out_aux2.hw }, { .hw = &gpll7_out_main.hw }, { .hw = &gpll4_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_14[] = { { P_BI_TCXO, 0 }, { P_SLEEP_CLK, 5 }, }; static const struct clk_parent_data gcc_parent_data_14[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "sleep_clk" }, }; static const struct freq_tbl ftbl_gcc_camss_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0), F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0), { } }; static struct clk_rcg2 gcc_camss_ahb_clk_src = { .cmd_rcgr = 0x56088, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_9, .freq_tbl = ftbl_gcc_camss_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_ahb_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0), F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), { } }; static struct clk_rcg2 gcc_camss_cci_clk_src = { .cmd_rcgr = 0x52004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_5, .freq_tbl = ftbl_gcc_camss_cci_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_cci_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_cpp_clk_src[] = { F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0), F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0), F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 gcc_camss_cpp_clk_src = { .cmd_rcgr = 0x560c8, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_10, .freq_tbl = ftbl_gcc_camss_cpp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_cpp_clk_src", .parent_data = gcc_parent_data_10, .num_parents = ARRAY_SIZE(gcc_parent_data_10), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_csi0_clk_src[] = { F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0), F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0), { } }; static struct clk_rcg2 gcc_camss_csi0_clk_src = { .cmd_rcgr = 0x55030, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_camss_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), { } }; static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { .cmd_rcgr = 0x53004, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0phytimer_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_csi1_clk_src = { .cmd_rcgr = 0x5506c, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_camss_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { .cmd_rcgr = 0x53024, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1phytimer_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_csi2_clk_src = { .cmd_rcgr = 0x550a4, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_camss_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { .cmd_rcgr = 0x53044, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2phytimer_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_csi3_clk_src = { .cmd_rcgr = 0x550e0, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_camss_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi3_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_csiphy_clk_src[] = { F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), { } }; static struct clk_rcg2 gcc_camss_csiphy_clk_src = { .cmd_rcgr = 0x55000, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_11, .freq_tbl = ftbl_gcc_camss_csiphy_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_csiphy_clk_src", .parent_data = gcc_parent_data_11, .num_parents = ARRAY_SIZE(gcc_parent_data_11), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_gp0_clk_src[] = { F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), { } }; static struct clk_rcg2 gcc_camss_gp0_clk_src = { .cmd_rcgr = 0x50000, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_7, .freq_tbl = ftbl_gcc_camss_gp0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_gp0_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_gp1_clk_src = { .cmd_rcgr = 0x5001c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_7, .freq_tbl = ftbl_gcc_camss_gp0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_gp1_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_jpeg_clk_src[] = { F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0), F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0), F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0), { } }; static struct clk_rcg2 gcc_camss_jpeg_clk_src = { .cmd_rcgr = 0x52028, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_12, .freq_tbl = ftbl_gcc_camss_jpeg_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_jpeg_clk_src", .parent_data = gcc_parent_data_12, .num_parents = ARRAY_SIZE(gcc_parent_data_12), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), { } }; static struct clk_rcg2 gcc_camss_mclk0_clk_src = { .cmd_rcgr = 0x51000, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_4, .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk0_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_mclk1_clk_src = { .cmd_rcgr = 0x5101c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_4, .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk1_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_mclk2_clk_src = { .cmd_rcgr = 0x51038, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_4, .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk2_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_mclk3_clk_src = { .cmd_rcgr = 0x51054, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_4, .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk3_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_camss_vfe0_clk_src[] = { F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0), F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0), F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 gcc_camss_vfe0_clk_src = { .cmd_rcgr = 0x54010, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_8, .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe0_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_camss_vfe1_clk_src = { .cmd_rcgr = 0x54048, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_8, .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe1_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), { } }; static struct clk_rcg2 gcc_gp1_clk_src = { .cmd_rcgr = 0x4d004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_gp2_clk_src = { .cmd_rcgr = 0x4e004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_gp3_clk_src = { .cmd_rcgr = 0x4f004, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), { } }; static struct clk_rcg2 gcc_pdm2_clk_src = { .cmd_rcgr = 0x20010, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pdm2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), F(19200000, P_BI_TCXO, 1, 0, 0), F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), { } }; static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { .cmd_rcgr = 0x1f148, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { .cmd_rcgr = 0x1f278, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { .cmd_rcgr = 0x1f3a8, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { .cmd_rcgr = 0x1f4d8, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { .cmd_rcgr = 0x1f608, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { .cmd_rcgr = 0x1f738, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { .cmd_rcgr = 0x39148, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { .cmd_rcgr = 0x39278, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { .cmd_rcgr = 0x393a8, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { .cmd_rcgr = 0x394d8, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { .cmd_rcgr = 0x39608, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, }; static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { .cmd_rcgr = 0x39738, .mnd_width = 16, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, }; static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { F(144000, P_BI_TCXO, 16, 3, 25), F(400000, P_BI_TCXO, 12, 1, 4), F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .cmd_rcgr = 0x38028, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_floor_ops, }, }; static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), { } }; static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .cmd_rcgr = 0x38010, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { F(400000, P_BI_TCXO, 12, 1, 4), F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), { } }; static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .cmd_rcgr = 0x1e00c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_13, .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_13, .num_parents = ARRAY_SIZE(gcc_parent_data_13), .ops = &clk_rcg2_floor_ops, }, }; static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), { } }; static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .cmd_rcgr = 0x45020, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), { } }; static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .cmd_rcgr = 0x45048, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { F(9600000, P_BI_TCXO, 2, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .cmd_rcgr = 0x4507c, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0), F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), { } }; static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .cmd_rcgr = 0x45060, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), { } }; static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .cmd_rcgr = 0x1a01c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0), F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), { } }; static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .cmd_rcgr = 0x1a034, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .cmd_rcgr = 0x1a060, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_14, .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_14, .num_parents = ARRAY_SIZE(gcc_parent_data_14), .ops = &clk_rcg2_ops, }, }; static struct clk_rcg2 gcc_vs_ctrl_clk_src = { .cmd_rcgr = 0x42030, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_5, .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_vs_ctrl_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_rcg2_ops, }, }; static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0), F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0), { } }; static struct clk_rcg2 gcc_vsensor_clk_src = { .cmd_rcgr = 0x42018, .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_5, .freq_tbl = ftbl_gcc_vsensor_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_vsensor_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_rcg2_ops, }, }; static struct clk_branch gcc_ahb2phy_csi_clk = { .halt_reg = 0x1d004, .halt_check = BRANCH_HALT, .hwcg_reg = 0x1d004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x1d004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ahb2phy_csi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ahb2phy_usb_clk = { .halt_reg = 0x1d008, .halt_check = BRANCH_HALT, .hwcg_reg = 0x1d008, .hwcg_bit = 1, .clkr = { .enable_reg = 0x1d008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ahb2phy_usb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_apc_vs_clk = { .halt_reg = 0x4204c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4204c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_apc_vs_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_bimc_gpu_axi_clk = { .halt_reg = 0x71154, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x71154, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_bimc_gpu_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_boot_rom_ahb_clk = { .halt_reg = 0x23004, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x23004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_boot_rom_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camera_ahb_clk = { .halt_reg = 0x17008, .halt_check = BRANCH_HALT_DELAY, .hwcg_reg = 0x17008, .hwcg_bit = 1, .clkr = { .enable_reg = 0x17008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camera_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camera_xo_clk = { .halt_reg = 0x17028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x17028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camera_xo_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cci_ahb_clk = { .halt_reg = 0x52020, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x52020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cci_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cci_clk = { .halt_reg = 0x5201c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5201c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cci_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_cci_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cphy_csid0_clk = { .halt_reg = 0x5504c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5504c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_csid0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csiphy_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cphy_csid1_clk = { .halt_reg = 0x55088, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55088, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_csid1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csiphy_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cphy_csid2_clk = { .halt_reg = 0x550c0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x550c0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_csid2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csiphy_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cphy_csid3_clk = { .halt_reg = 0x550fc, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x550fc, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_csid3_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csiphy_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cpp_ahb_clk = { .halt_reg = 0x560e8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x560e8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cpp_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cpp_axi_clk = { .halt_reg = 0x560f4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x560f4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cpp_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cpp_clk = { .halt_reg = 0x560e0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x560e0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cpp_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_cpp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_cpp_vbif_ahb_clk = { .halt_reg = 0x560f0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x560f0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cpp_vbif_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi0_ahb_clk = { .halt_reg = 0x55050, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55050, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi0_clk = { .halt_reg = 0x55048, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55048, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi0phytimer_clk = { .halt_reg = 0x5301c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5301c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi0pix_clk = { .halt_reg = 0x55060, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55060, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0pix_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi0rdi_clk = { .halt_reg = 0x55058, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55058, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0rdi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi1_ahb_clk = { .halt_reg = 0x5508c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5508c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi1_clk = { .halt_reg = 0x55084, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55084, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi1phytimer_clk = { .halt_reg = 0x5303c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5303c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi1pix_clk = { .halt_reg = 0x5509c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5509c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1pix_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi1rdi_clk = { .halt_reg = 0x55094, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55094, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1rdi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi2_ahb_clk = { .halt_reg = 0x550c4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x550c4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi2_clk = { .halt_reg = 0x550bc, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x550bc, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi2phytimer_clk = { .halt_reg = 0x5305c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5305c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi2pix_clk = { .halt_reg = 0x550d4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x550d4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2pix_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi2rdi_clk = { .halt_reg = 0x550cc, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x550cc, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2rdi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi3_ahb_clk = { .halt_reg = 0x55100, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55100, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi3_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi3_clk = { .halt_reg = 0x550f8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x550f8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi3_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi3pix_clk = { .halt_reg = 0x55110, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55110, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi3pix_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi3rdi_clk = { .halt_reg = 0x55108, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55108, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi3rdi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csi3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi_vfe0_clk = { .halt_reg = 0x54074, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54074, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi_vfe0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_vfe0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csi_vfe1_clk = { .halt_reg = 0x54080, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54080, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi_vfe1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_vfe1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csiphy0_clk = { .halt_reg = 0x55018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csiphy0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csiphy_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csiphy1_clk = { .halt_reg = 0x5501c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5501c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csiphy1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csiphy_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_csiphy2_clk = { .halt_reg = 0x55020, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x55020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csiphy2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_csiphy_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_gp0_clk = { .halt_reg = 0x50018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x50018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_gp0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_gp0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_gp1_clk = { .halt_reg = 0x50034, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x50034, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_gp1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_ispif_ahb_clk = { .halt_reg = 0x540a4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x540a4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_ispif_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_jpeg_ahb_clk = { .halt_reg = 0x52048, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x52048, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_jpeg_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_jpeg_axi_clk = { .halt_reg = 0x5204c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5204c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_jpeg_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_jpeg_clk = { .halt_reg = 0x52040, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x52040, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_jpeg_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_mclk0_clk = { .halt_reg = 0x51018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x51018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_mclk1_clk = { .halt_reg = 0x51034, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x51034, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_mclk2_clk = { .halt_reg = 0x51050, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x51050, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_mclk3_clk = { .halt_reg = 0x5106c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5106c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk3_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_micro_ahb_clk = { .halt_reg = 0x560b0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x560b0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_micro_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_throttle_nrt_axi_clk = { .halt_reg = 0x560a4, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_throttle_nrt_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_throttle_rt_axi_clk = { .halt_reg = 0x560a8, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_throttle_rt_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_top_ahb_clk = { .halt_reg = 0x560a0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x560a0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_top_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe0_ahb_clk = { .halt_reg = 0x54034, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54034, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe0_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe0_clk = { .halt_reg = 0x54028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_vfe0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe0_stream_clk = { .halt_reg = 0x54030, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54030, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe0_stream_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_vfe0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe1_ahb_clk = { .halt_reg = 0x5406c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5406c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe1_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe1_clk = { .halt_reg = 0x54060, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54060, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_vfe1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe1_stream_clk = { .halt_reg = 0x54068, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54068, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe1_stream_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_vfe1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe_tsctr_clk = { .halt_reg = 0x5409c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5409c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe_tsctr_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe_vbif_ahb_clk = { .halt_reg = 0x5408c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5408c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe_vbif_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_camss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_camss_vfe_vbif_axi_clk = { .halt_reg = 0x54090, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x54090, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe_vbif_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ce1_ahb_clk = { .halt_reg = 0x2700c, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x2700c, .hwcg_bit = 1, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gcc_ce1_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ce1_axi_clk = { .halt_reg = 0x27008, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_ce1_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ce1_clk = { .halt_reg = 0x27004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gcc_ce1_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .halt_reg = 0x1a084, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1a084, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_prim_axi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_cpuss_gnoc_clk = { .halt_reg = 0x2b004, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x2b004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_gnoc_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_disp_ahb_clk = { .halt_reg = 0x1700c, .halt_check = BRANCH_HALT, .hwcg_reg = 0x1700c, .hwcg_bit = 1, .clkr = { .enable_reg = 0x1700c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_disp_gpll0_div_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(20), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_gpll0_div_clk_src", .parent_hws = (const struct clk_hw*[]){ &gpll0_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_disp_hf_axi_clk = { .halt_reg = 0x17020, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x17020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_hf_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_disp_throttle_core_clk = { .halt_reg = 0x17064, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_throttle_core_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_disp_xo_clk = { .halt_reg = 0x1702c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1702c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_xo_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4d000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gp2_clk = { .halt_reg = 0x4e000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4e000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gp3_clk = { .halt_reg = 0x4f000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4f000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_cfg_ahb_clk = { .halt_reg = 0x36004, .halt_check = BRANCH_HALT, .hwcg_reg = 0x36004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x36004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_cfg_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_clk_src", .parent_hws = (const struct clk_hw*[]){ &gpll0_out_early.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_div_clk_src", .parent_hws = (const struct clk_hw*[]){ &gpll0_out_aux2.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .halt_reg = 0x3600c, .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x3600c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_memnoc_gfx_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .halt_reg = 0x36018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x36018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_snoc_dvm_gfx_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_throttle_core_clk = { .halt_reg = 0x36048, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(31), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_throttle_core_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_gpu_throttle_xo_clk = { .halt_reg = 0x36044, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x36044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_throttle_xo_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_mss_vs_clk = { .halt_reg = 0x42048, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x42048, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_vs_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x2000c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2000c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm_ahb_clk = { .halt_reg = 0x20004, .halt_check = BRANCH_HALT, .hwcg_reg = 0x20004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x20004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_pdm_xo4_clk = { .halt_reg = 0x20008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x20008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_xo4_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_prng_ahb_clk = { .halt_reg = 0x21004, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x21004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_prng_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { .halt_reg = 0x17014, .halt_check = BRANCH_HALT, .hwcg_reg = 0x17014, .hwcg_bit = 1, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qmip_camera_nrt_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { .halt_reg = 0x17060, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x17060, .hwcg_bit = 1, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gcc_qmip_camera_rt_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qmip_disp_ahb_clk = { .halt_reg = 0x17018, .halt_check = BRANCH_HALT, .hwcg_reg = 0x17018, .hwcg_bit = 1, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_qmip_disp_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { .halt_reg = 0x36040, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x36040, .hwcg_bit = 1, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_qmip_gpu_cfg_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { .halt_reg = 0x17010, .halt_check = BRANCH_HALT, .hwcg_reg = 0x17010, .hwcg_bit = 1, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_qmip_video_vcodec_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { .halt_reg = 0x1f014, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_core_2x_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_core_clk = { .halt_reg = 0x1f00c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_core_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .halt_reg = 0x1f144, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .halt_reg = 0x1f274, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .halt_reg = 0x1f3a4, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .halt_reg = 0x1f4d4, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .halt_reg = 0x1f604, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .halt_reg = 0x1f734, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { .halt_reg = 0x39014, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(18), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_core_2x_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_core_clk = { .halt_reg = 0x3900c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(19), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_core_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .halt_reg = 0x39144, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .halt_reg = 0x39274, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .halt_reg = 0x393a4, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(24), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .halt_reg = 0x394d4, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .halt_reg = 0x39604, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .halt_reg = 0x39734, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { .halt_reg = 0x1f004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(6), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap_0_m_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { .halt_reg = 0x1f008, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x1f008, .hwcg_bit = 1, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap_0_s_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { .halt_reg = 0x39004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(20), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap_1_m_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { .halt_reg = 0x39008, .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x39008, .hwcg_bit = 1, .clkr = { .enable_reg = 0x7900c, .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap_1_s_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc1_ahb_clk = { .halt_reg = 0x38008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x38008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc1_apps_clk = { .halt_reg = 0x38004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x38004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc1_ice_core_clk = { .halt_reg = 0x3800c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x3800c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc2_ahb_clk = { .halt_reg = 0x1e008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1e008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sdcc2_apps_clk = { .halt_reg = 0x1e004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1e004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = { .halt_reg = 0x1050c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1050c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_compute_sf_axi_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { .halt_reg = 0x2b06c, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_cpuss_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x45098, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_ufs_phy_axi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { .halt_reg = 0x1a080, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1a080, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_usb3_prim_axi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_mem_clkref_clk = { .halt_reg = 0x8c000, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x8c000, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_mem_clkref_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_ahb_clk = { .halt_reg = 0x45014, .halt_check = BRANCH_HALT, .hwcg_reg = 0x45014, .hwcg_bit = 1, .clkr = { .enable_reg = 0x45014, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_axi_clk = { .halt_reg = 0x45010, .halt_check = BRANCH_HALT, .hwcg_reg = 0x45010, .hwcg_bit = 1, .clkr = { .enable_reg = 0x45010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_ice_core_clk = { .halt_reg = 0x45044, .halt_check = BRANCH_HALT, .hwcg_reg = 0x45044, .hwcg_bit = 1, .clkr = { .enable_reg = 0x45044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .halt_reg = 0x45078, .halt_check = BRANCH_HALT, .hwcg_reg = 0x45078, .hwcg_bit = 1, .clkr = { .enable_reg = 0x45078, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { .halt_reg = 0x4501c, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x4501c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_rx_symbol_0_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { .halt_reg = 0x45018, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x45018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_tx_symbol_0_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .halt_reg = 0x45040, .halt_check = BRANCH_HALT, .hwcg_reg = 0x45040, .hwcg_bit = 1, .clkr = { .enable_reg = 0x45040, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb30_prim_master_clk = { .halt_reg = 0x1a010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1a010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { .halt_reg = 0x1a018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1a018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb30_prim_sleep_clk = { .halt_reg = 0x1a014, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1a014, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_sleep_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb3_prim_clkref_clk = { .halt_reg = 0x80278, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x80278, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_clkref_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .halt_reg = 0x1a054, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1a054, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_com_aux_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x1a058, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_pipe_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_vdda_vs_clk = { .halt_reg = 0x4200c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x4200c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_vdda_vs_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_vddcx_vs_clk = { .halt_reg = 0x42004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x42004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_vddcx_vs_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_vddmx_vs_clk = { .halt_reg = 0x42008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x42008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_vddmx_vs_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_video_ahb_clk = { .halt_reg = 0x17004, .halt_check = BRANCH_HALT, .hwcg_reg = 0x17004, .hwcg_bit = 1, .clkr = { .enable_reg = 0x17004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_video_axi0_clk = { .halt_reg = 0x1701c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1701c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_axi0_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_video_throttle_core_clk = { .halt_reg = 0x17068, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x79004, .enable_mask = BIT(28), .hw.init = &(struct clk_init_data){ .name = "gcc_video_throttle_core_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_video_xo_clk = { .halt_reg = 0x17024, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x17024, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_xo_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_vs_ctrl_ahb_clk = { .halt_reg = 0x42014, .halt_check = BRANCH_HALT, .hwcg_reg = 0x42014, .hwcg_bit = 1, .clkr = { .enable_reg = 0x42014, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_vs_ctrl_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_vs_ctrl_clk = { .halt_reg = 0x42010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x42010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_vs_ctrl_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_vs_ctrl_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_wcss_vs_clk = { .halt_reg = 0x42050, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x42050, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_wcss_vs_clk", .parent_hws = (const struct clk_hw*[]){ &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct gdsc usb30_prim_gdsc = { .gdscr = 0x1a004, .pd = { .name = "usb30_prim_gdsc", }, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc ufs_phy_gdsc = { .gdscr = 0x45004, .pd = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc camss_vfe0_gdsc = { .gdscr = 0x54004, .pd = { .name = "camss_vfe0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc camss_vfe1_gdsc = { .gdscr = 0x5403c, .pd = { .name = "camss_vfe1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc camss_top_gdsc = { .gdscr = 0x5607c, .pd = { .name = "camss_top_gdsc", }, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc cam_cpp_gdsc = { .gdscr = 0x560bc, .pd = { .name = "cam_cpp_gdsc", }, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { .gdscr = 0x7d060, .pd = { .name = "hlos1_vote_turing_mmu_tbu1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { .gdscr = 0x80074, .pd = { .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { .gdscr = 0x80084, .pd = { .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { .gdscr = 0x80094, .pd = { .name = "hlos1_vote_turing_mmu_tbu0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; static struct gdsc *gcc_sm6125_gdscs[] = { [USB30_PRIM_GDSC] = &usb30_prim_gdsc, [UFS_PHY_GDSC] = &ufs_phy_gdsc, [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc, [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc, [CAMSS_TOP_GDSC] = &camss_top_gdsc, [CAM_CPP_GDSC] = &cam_cpp_gdsc, [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, }; static struct clk_hw *gcc_sm6125_hws[] = { [GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw, [GPLL0_OUT_MAIN] = &gpll0_out_main.hw, [GPLL6_OUT_MAIN] = &gpll6_out_main.hw, [GPLL7_OUT_MAIN] = &gpll7_out_main.hw, [GPLL8_OUT_MAIN] = &gpll8_out_main.hw, [GPLL9_OUT_MAIN] = &gpll9_out_main.hw, }; static struct clk_regmap *gcc_sm6125_clocks[] = { [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AHB_CLK_SRC] = &gcc_camss_ahb_clk_src.clkr, [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, [GCC_CAMSS_CPHY_CSID0_CLK] = &gcc_camss_cphy_csid0_clk.clkr, [GCC_CAMSS_CPHY_CSID1_CLK] = &gcc_camss_cphy_csid1_clk.clkr, [GCC_CAMSS_CPHY_CSID2_CLK] = &gcc_camss_cphy_csid2_clk.clkr, [GCC_CAMSS_CPHY_CSID3_CLK] = &gcc_camss_cphy_csid3_clk.clkr, [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, [GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr, [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, [GCC_CAMSS_CPP_CLK_SRC] = &gcc_camss_cpp_clk_src.clkr, [GCC_CAMSS_CPP_VBIF_AHB_CLK] = &gcc_camss_cpp_vbif_ahb_clk.clkr, [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, [GCC_CAMSS_CSI0_CLK_SRC] = &gcc_camss_csi0_clk_src.clkr, [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, [GCC_CAMSS_CSI1_CLK_SRC] = &gcc_camss_csi1_clk_src.clkr, [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr, [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr, [GCC_CAMSS_CSI2_CLK_SRC] = &gcc_camss_csi2_clk_src.clkr, [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr, [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr, [GCC_CAMSS_CSI3_AHB_CLK] = &gcc_camss_csi3_ahb_clk.clkr, [GCC_CAMSS_CSI3_CLK] = &gcc_camss_csi3_clk.clkr, [GCC_CAMSS_CSI3_CLK_SRC] = &gcc_camss_csi3_clk_src.clkr, [GCC_CAMSS_CSI3PIX_CLK] = &gcc_camss_csi3pix_clk.clkr, [GCC_CAMSS_CSI3RDI_CLK] = &gcc_camss_csi3rdi_clk.clkr, [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr, [GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr, [GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr, [GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr, [GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr, [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, [GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr, [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, [GCC_CAMSS_GP1_CLK_SRC] = &gcc_camss_gp1_clk_src.clkr, [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, [GCC_CAMSS_JPEG_CLK] = &gcc_camss_jpeg_clk.clkr, [GCC_CAMSS_JPEG_CLK_SRC] = &gcc_camss_jpeg_clk_src.clkr, [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, [GCC_CAMSS_THROTTLE_NRT_AXI_CLK] = &gcc_camss_throttle_nrt_axi_clk.clkr, [GCC_CAMSS_THROTTLE_RT_AXI_CLK] = &gcc_camss_throttle_rt_axi_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr, [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, [GCC_CAMSS_VFE0_CLK_SRC] = &gcc_camss_vfe0_clk_src.clkr, [GCC_CAMSS_VFE0_STREAM_CLK] = &gcc_camss_vfe0_stream_clk.clkr, [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr, [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr, [GCC_CAMSS_VFE1_CLK_SRC] = &gcc_camss_vfe1_clk_src.clkr, [GCC_CAMSS_VFE1_STREAM_CLK] = &gcc_camss_vfe1_stream_clk.clkr, [GCC_CAMSS_VFE_TSCTR_CLK] = &gcc_camss_vfe_tsctr_clk.clkr, [GCC_CAMSS_VFE_VBIF_AHB_CLK] = &gcc_camss_vfe_vbif_ahb_clk.clkr, [GCC_CAMSS_VFE_VBIF_AXI_CLK] = &gcc_camss_vfe_vbif_axi_clk.clkr, [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, [GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr, [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, [GCC_SYS_NOC_COMPUTE_SF_AXI_CLK] = &gcc_sys_noc_compute_sf_axi_clk.clkr, [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, [GCC_WCSS_VS_CLK] = &gcc_wcss_vs_clk.clkr, [GPLL0_OUT_EARLY] = &gpll0_out_early.clkr, [GPLL3_OUT_EARLY] = &gpll3_out_early.clkr, [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, [GPLL5_OUT_MAIN] = &gpll5_out_main.clkr, [GPLL6_OUT_EARLY] = &gpll6_out_early.clkr, [GPLL7_OUT_EARLY] = &gpll7_out_early.clkr, [GPLL8_OUT_EARLY] = &gpll8_out_early.clkr, [GPLL9_OUT_EARLY] = &gpll9_out_early.clkr, [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, }; static const struct qcom_reset_map gcc_sm6125_resets[] = { [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, [GCC_UFS_PHY_BCR] = { 0x45000 }, [GCC_USB30_PRIM_BCR] = { 0x1a000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, [GCC_CAMSS_MICRO_BCR] = { 0x560ac }, }; static struct clk_rcg_dfs_data gcc_dfs_clocks[] = { DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), }; static const struct regmap_config gcc_sm6125_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0xc7000, .fast_io = true, }; static const struct qcom_cc_desc gcc_sm6125_desc = { .config = &gcc_sm6125_regmap_config, .clks = gcc_sm6125_clocks, .num_clks = ARRAY_SIZE(gcc_sm6125_clocks), .clk_hws = gcc_sm6125_hws, .num_clk_hws = ARRAY_SIZE(gcc_sm6125_hws), .resets = gcc_sm6125_resets, .num_resets = ARRAY_SIZE(gcc_sm6125_resets), .gdscs = gcc_sm6125_gdscs, .num_gdscs = ARRAY_SIZE(gcc_sm6125_gdscs), }; static const struct of_device_id gcc_sm6125_match_table[] = { { .compatible = "qcom,gcc-sm6125" }, { } }; MODULE_DEVICE_TABLE(of, gcc_sm6125_match_table); static int gcc_sm6125_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; regmap = qcom_cc_map(pdev, &gcc_sm6125_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); /* * Disable the GPLL0 active input to video block via * MISC registers. */ regmap_update_bits(regmap, 0x80258, 0x1, 0x1); /* * Enable DUAL_EDGE mode for MCLK RCGs * This is required to enable MND divider mode */ regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000); regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000); regmap_update_bits(regmap, 0x5103c, 0x3000, 0x2000); regmap_update_bits(regmap, 0x51058, 0x3000, 0x2000); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) return ret; return qcom_cc_really_probe(&pdev->dev, &gcc_sm6125_desc, regmap); } static struct platform_driver gcc_sm6125_driver = { .probe = gcc_sm6125_probe, .driver = { .name = "gcc-sm6125", .of_match_table = gcc_sm6125_match_table, }, }; static int __init gcc_sm6125_init(void) { return platform_driver_register(&gcc_sm6125_driver); } subsys_initcall(gcc_sm6125_init); static void __exit gcc_sm6125_exit(void) { platform_driver_unregister(&gcc_sm6125_driver); } module_exit(gcc_sm6125_exit); MODULE_DESCRIPTION("QTI GCC SM6125 Driver"); MODULE_LICENSE("GPL v2");
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