Contributors: 10
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Ville Syrjälä |
225 |
55.42% |
15 |
50.00% |
| Jani Nikula |
85 |
20.94% |
5 |
16.67% |
| Maarten Lankhorst |
40 |
9.85% |
2 |
6.67% |
| Jesse Barnes |
19 |
4.68% |
1 |
3.33% |
| Daniel Vetter |
12 |
2.96% |
1 |
3.33% |
| Matt Roper |
12 |
2.96% |
2 |
6.67% |
| Michal Wajdeczko |
6 |
1.48% |
1 |
3.33% |
| Dave Airlie |
4 |
0.99% |
1 |
3.33% |
| Clint Taylor |
2 |
0.49% |
1 |
3.33% |
| Vandita Kulkarni |
1 |
0.25% |
1 |
3.33% |
| Total |
406 |
|
30 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2021 Intel Corporation
*/
#ifndef _INTEL_PCH_DISPLAY_H_
#define _INTEL_PCH_DISPLAY_H_
#include <linux/types.h>
enum pipe;
struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_link_m_n;
#ifdef I915
bool intel_has_pch_trancoder(struct drm_i915_private *i915,
enum pipe pch_transcoder);
enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
void ilk_pch_pre_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_post_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
void lpt_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void lpt_pch_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
struct intel_link_m_n *m_n);
void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
struct intel_link_m_n *m_n);
void intel_pch_sanitize(struct drm_i915_private *i915);
#else
static inline bool intel_has_pch_trancoder(struct drm_i915_private *i915,
enum pipe pch_transcoder)
{
return false;
}
static inline int intel_crtc_pch_transcoder(struct intel_crtc *crtc)
{
return 0;
}
static inline void ilk_pch_pre_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
}
static inline void ilk_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
}
static inline void ilk_pch_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
}
static inline void ilk_pch_post_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
}
static inline void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
{
}
static inline void lpt_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
}
static inline void lpt_pch_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
}
static inline void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
{
}
static inline void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
}
static inline void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
}
static inline void intel_pch_sanitize(struct drm_i915_private *i915)
{
}
#endif
#endif