| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Jacopo Mondi | 48375 | 100.00% | 1 | 100.00% |
| Total | 48375 | 1 |
// SPDX-License-Identifier: GPL-2.0 /* * V4L2 sensor driver for OmniVision OV64A40 * * Copyright (C) 2023 Ideas On Board Oy * Copyright (C) 2023 Arducam */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pm_runtime.h> #include <linux/regulator/consumer.h> #include <media/v4l2-cci.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-event.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-mediabus.h> #include <media/v4l2-subdev.h> #define OV64A40_XCLK_FREQ 24000000 #define OV64A40_NATIVE_WIDTH 9286 #define OV64A40_NATIVE_HEIGHT 6976 #define OV64A40_PIXEL_ARRAY_TOP 0 #define OV64A40_PIXEL_ARRAY_LEFT 0 #define OV64A40_PIXEL_ARRAY_WIDTH 9248 #define OV64A40_PIXEL_ARRAY_HEIGHT 6944 #define OV64A40_PIXEL_RATE 300000000 #define OV64A40_LINK_FREQ_360M 360000000 #define OV64A40_LINK_FREQ_456M 456000000 #define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301) #define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303) #define OV64A40_PLL1_MULTIPLIER CCI_REG16(0x0304) #define OV64A40_PLL1_M_DIV CCI_REG8(0x0307) #define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320) #define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323) #define OV64A40_PLL2_MULTIPLIER CCI_REG16(0x0324) #define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326) #define OV64A40_PLL2_DIVDAC CCI_REG8(0x0329) #define OV64A40_PLL2_DIVSP CCI_REG8(0x032d) #define OV64A40_PLL2_DACPREDIV CCI_REG8(0x032e) /* TODO: validate vblank_min, it's not characterized in the datasheet. */ #define OV64A40_VBLANK_MIN 128 #define OV64A40_VTS_MAX 0xffffff #define OV64A40_REG_MEC_LONG_EXPO CCI_REG24(0x3500) #define OV64A40_EXPOSURE_MIN 16 #define OV64A40_EXPOSURE_MARGIN 32 #define OV64A40_REG_MEC_LONG_GAIN CCI_REG16(0x3508) #define OV64A40_ANA_GAIN_MIN 0x80 #define OV64A40_ANA_GAIN_MAX 0x7ff #define OV64A40_ANA_GAIN_DEFAULT 0x80 #define OV64A40_REG_TIMING_CTRL0 CCI_REG16(0x3800) #define OV64A40_REG_TIMING_CTRL2 CCI_REG16(0x3802) #define OV64A40_REG_TIMING_CTRL4 CCI_REG16(0x3804) #define OV64A40_REG_TIMING_CTRL6 CCI_REG16(0x3806) #define OV64A40_REG_TIMING_CTRL8 CCI_REG16(0x3808) #define OV64A40_REG_TIMING_CTRLA CCI_REG16(0x380a) #define OV64A40_REG_TIMING_CTRLC CCI_REG16(0x380c) #define OV64A40_REG_TIMING_CTRLE CCI_REG16(0x380e) #define OV64A40_REG_TIMING_CTRL10 CCI_REG16(0x3810) #define OV64A40_REG_TIMING_CTRL12 CCI_REG16(0x3812) /* * Careful: a typo in the datasheet calls this register * OV64A40_REG_TIMING_CTRL20. */ #define OV64A40_REG_TIMING_CTRL14 CCI_REG8(0x3814) #define OV64A40_REG_TIMING_CTRL15 CCI_REG8(0x3815) #define OV64A40_ODD_INC_SHIFT 4 #define OV64A40_SKIPPING_CONFIG(_odd, _even) \ (((_odd) << OV64A40_ODD_INC_SHIFT) | (_even)) #define OV64A40_REG_TIMING_CTRL_20 CCI_REG8(0x3820) #define OV64A40_TIMING_CTRL_20_VFLIP BIT(2) #define OV64A40_TIMING_CTRL_20_VBIN BIT(1) #define OV64A40_REG_TIMING_CTRL_21 CCI_REG8(0x3821) #define OV64A40_TIMING_CTRL_21_HBIN BIT(4) #define OV64A40_TIMING_CTRL_21_HFLIP BIT(2) #define OV64A40_TIMING_CTRL_21_DSPEED BIT(0) #define OV64A40_TIMING_CTRL_21_HBIN_CONF \ (OV64A40_TIMING_CTRL_21_HBIN | \ OV64A40_TIMING_CTRL_21_DSPEED) #define OV64A40_REG_TIMINGS_VTS_HIGH CCI_REG8(0x3840) #define OV64A40_REG_TIMINGS_VTS_MID CCI_REG8(0x380e) #define OV64A40_REG_TIMINGS_VTS_LOW CCI_REG8(0x380f) /* The test pattern control is weirdly named PRE_ISP_2325_D2V2_TOP_1 in TRM. */ #define OV64A40_REG_TEST_PATTERN CCI_REG8(0x50c1) #define OV64A40_TEST_PATTERN_DISABLED 0x00 #define OV64A40_TEST_PATTERN_TYPE1 BIT(0) #define OV64A40_TEST_PATTERN_TYPE2 (BIT(4) | BIT(0)) #define OV64A40_TEST_PATTERN_TYPE3 (BIT(5) | BIT(0)) #define OV64A40_TEST_PATTERN_TYPE4 (BIT(5) | BIT(4) | BIT(0)) #define OV64A40_REG_CHIP_ID CCI_REG24(0x300a) #define OV64A40_CHIP_ID 0x566441 #define OV64A40_REG_SMIA CCI_REG8(0x0100) #define OV64A40_REG_SMIA_STREAMING BIT(0) enum ov64a40_link_freq_ids { OV64A40_LINK_FREQ_456M_ID, OV64A40_LINK_FREQ_360M_ID, OV64A40_NUM_LINK_FREQ, }; static const char * const ov64a40_supply_names[] = { /* Supplies can be enabled in any order */ "avdd", /* Analog (2.8V) supply */ "dovdd", /* Digital Core (1.8V) supply */ "dvdd", /* IF (1.1V) supply */ }; static const char * const ov64a40_test_pattern_menu[] = { "Disabled", "Type1", "Type2", "Type3", "Type4", }; static const int ov64a40_test_pattern_val[] = { OV64A40_TEST_PATTERN_DISABLED, OV64A40_TEST_PATTERN_TYPE1, OV64A40_TEST_PATTERN_TYPE2, OV64A40_TEST_PATTERN_TYPE3, OV64A40_TEST_PATTERN_TYPE4, }; static const unsigned int ov64a40_mbus_codes[] = { MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10, }; static const struct cci_reg_sequence ov64a40_init[] = { { CCI_REG8(0x0103), 0x01 }, { CCI_REG8(0x0301), 0x88 }, { CCI_REG8(0x0304), 0x00 }, { CCI_REG8(0x0305), 0x96 }, { CCI_REG8(0x0306), 0x03 }, { CCI_REG8(0x0307), 0x00 }, { CCI_REG8(0x0345), 0x2c }, { CCI_REG8(0x034a), 0x02 }, { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x0350), 0xc0 }, { CCI_REG8(0x0360), 0x09 }, { CCI_REG8(0x3012), 0x31 }, { CCI_REG8(0x3015), 0xf0 }, { CCI_REG8(0x3017), 0xf0 }, { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 }, { CCI_REG8(0x3022), 0xf0 }, { CCI_REG8(0x3400), 0x08 }, { CCI_REG8(0x3608), 0x41 }, { CCI_REG8(0x3421), 0x02 }, { CCI_REG8(0x3500), 0x00 }, { CCI_REG8(0x3501), 0x00 }, { CCI_REG8(0x3502), 0x18 }, { CCI_REG8(0x3504), 0x0c }, { CCI_REG8(0x3508), 0x01 }, { CCI_REG8(0x3509), 0x00 }, { CCI_REG8(0x350a), 0x01 }, { CCI_REG8(0x350b), 0x00 }, { CCI_REG8(0x350b), 0x00 }, { CCI_REG8(0x3540), 0x00 }, { CCI_REG8(0x3541), 0x00 }, { CCI_REG8(0x3542), 0x08 }, { CCI_REG8(0x3548), 0x01 }, { CCI_REG8(0x3549), 0xa0 }, { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3580), 0x00 }, { CCI_REG8(0x3581), 0x00 }, { CCI_REG8(0x3582), 0x04 }, { CCI_REG8(0x3588), 0x01 }, { CCI_REG8(0x3589), 0xf0 }, { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x360d), 0x83 }, { CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3617), 0x31 }, { CCI_REG8(0x3623), 0x10 }, { CCI_REG8(0x3633), 0x03 }, { CCI_REG8(0x3634), 0x03 }, { CCI_REG8(0x3635), 0x77 }, { CCI_REG8(0x3640), 0x19 }, { CCI_REG8(0x3641), 0x80 }, { CCI_REG8(0x364d), 0x0f }, { CCI_REG8(0x3680), 0x80 }, { CCI_REG8(0x3682), 0x00 }, { CCI_REG8(0x3683), 0x00 }, { CCI_REG8(0x3684), 0x07 }, { CCI_REG8(0x3688), 0x01 }, { CCI_REG8(0x3689), 0x08 }, { CCI_REG8(0x368a), 0x26 }, { CCI_REG8(0x368b), 0xc8 }, { CCI_REG8(0x368e), 0x70 }, { CCI_REG8(0x368f), 0x00 }, { CCI_REG8(0x3692), 0x04 }, { CCI_REG8(0x3693), 0x00 }, { CCI_REG8(0x3696), 0xd1 }, { CCI_REG8(0x3697), 0xe0 }, { CCI_REG8(0x3698), 0x80 }, { CCI_REG8(0x3699), 0x2b }, { CCI_REG8(0x369a), 0x00 }, { CCI_REG8(0x369d), 0x00 }, { CCI_REG8(0x369e), 0x14 }, { CCI_REG8(0x369f), 0x20 }, { CCI_REG8(0x36a5), 0x80 }, { CCI_REG8(0x36a6), 0x00 }, { CCI_REG8(0x36a7), 0x00 }, { CCI_REG8(0x36a8), 0x00 }, { CCI_REG8(0x36b5), 0x17 }, { CCI_REG8(0x3701), 0x30 }, { CCI_REG8(0x3706), 0x2b }, { CCI_REG8(0x3709), 0x8d }, { CCI_REG8(0x370b), 0x4f }, { CCI_REG8(0x3711), 0x00 }, { CCI_REG8(0x3712), 0x01 }, { CCI_REG8(0x3713), 0x00 }, { CCI_REG8(0x3720), 0x08 }, { CCI_REG8(0x3727), 0x22 }, { CCI_REG8(0x3728), 0x01 }, { CCI_REG8(0x375e), 0x00 }, { CCI_REG8(0x3760), 0x08 }, { CCI_REG8(0x3761), 0x10 }, { CCI_REG8(0x3762), 0x08 }, { CCI_REG8(0x3765), 0x10 }, { CCI_REG8(0x3766), 0x18 }, { CCI_REG8(0x376a), 0x08 }, { CCI_REG8(0x376b), 0x00 }, { CCI_REG8(0x376d), 0x1b }, { CCI_REG8(0x3791), 0x2b }, { CCI_REG8(0x3793), 0x2b }, { CCI_REG8(0x3795), 0x2b }, { CCI_REG8(0x3797), 0x4f }, { CCI_REG8(0x3799), 0x4f }, { CCI_REG8(0x379b), 0x4f }, { CCI_REG8(0x37a0), 0x22 }, { CCI_REG8(0x37da), 0x04 }, { CCI_REG8(0x37f9), 0x02 }, { CCI_REG8(0x37fa), 0x02 }, { CCI_REG8(0x37fb), 0x02 }, { CCI_REG8(0x3814), 0x11 }, { CCI_REG8(0x3815), 0x11 }, { CCI_REG8(0x3820), 0x40 }, { CCI_REG8(0x3821), 0x04 }, { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3823), 0x04 }, { CCI_REG8(0x3827), 0x08 }, { CCI_REG8(0x3828), 0x00 }, { CCI_REG8(0x382a), 0x81 }, { CCI_REG8(0x382e), 0x70 }, { CCI_REG8(0x3837), 0x10 }, { CCI_REG8(0x3839), 0x00 }, { CCI_REG8(0x383b), 0x00 }, { CCI_REG8(0x383c), 0x00 }, { CCI_REG8(0x383d), 0x10 }, { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0x8c }, { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x10 }, { CCI_REG8(0x3857), 0x10 }, { CCI_REG8(0x3858), 0x20 }, { CCI_REG8(0x3859), 0x20 }, { CCI_REG8(0x3894), 0x00 }, { CCI_REG8(0x3895), 0x00 }, { CCI_REG8(0x3896), 0x00 }, { CCI_REG8(0x3897), 0x00 }, { CCI_REG8(0x3900), 0x40 }, { CCI_REG8(0x3aed), 0x6e }, { CCI_REG8(0x3af1), 0x73 }, { CCI_REG8(0x3d86), 0x12 }, { CCI_REG8(0x3d87), 0x30 }, { CCI_REG8(0x3d8c), 0xab }, { CCI_REG8(0x3d8d), 0xb0 }, { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f01), 0x03 }, { CCI_REG8(0x4009), 0x01 }, { CCI_REG8(0x400e), 0xc6 }, { CCI_REG8(0x400f), 0x00 }, { CCI_REG8(0x4010), 0x28 }, { CCI_REG8(0x4011), 0x01 }, { CCI_REG8(0x4012), 0x0c }, { CCI_REG8(0x4015), 0x00 }, { CCI_REG8(0x4016), 0x1f }, { CCI_REG8(0x4017), 0x00 }, { CCI_REG8(0x4018), 0x07 }, { CCI_REG8(0x401a), 0x40 }, { CCI_REG8(0x4028), 0x01 }, { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4506), 0x01 }, { CCI_REG8(0x4508), 0x00 }, { CCI_REG8(0x4509), 0x35 }, { CCI_REG8(0x450a), 0x08 }, { CCI_REG8(0x450c), 0x00 }, { CCI_REG8(0x450d), 0x20 }, { CCI_REG8(0x450e), 0x00 }, { CCI_REG8(0x450f), 0x20 }, { CCI_REG8(0x451e), 0x00 }, { CCI_REG8(0x451f), 0x00 }, { CCI_REG8(0x4523), 0x00 }, { CCI_REG8(0x4526), 0x00 }, { CCI_REG8(0x4527), 0x18 }, { CCI_REG8(0x4580), 0x01 }, { CCI_REG8(0x4583), 0x00 }, { CCI_REG8(0x4584), 0x00 }, { CCI_REG8(0x45c0), 0xa1 }, { CCI_REG8(0x4602), 0x08 }, { CCI_REG8(0x4603), 0x05 }, { CCI_REG8(0x4606), 0x12 }, { CCI_REG8(0x4607), 0x30 }, { CCI_REG8(0x460b), 0x00 }, { CCI_REG8(0x460d), 0x00 }, { CCI_REG8(0x4640), 0x00 }, { CCI_REG8(0x4641), 0x24 }, { CCI_REG8(0x4643), 0x08 }, { CCI_REG8(0x4645), 0x14 }, { CCI_REG8(0x4648), 0x0a }, { CCI_REG8(0x4649), 0x06 }, { CCI_REG8(0x464a), 0x00 }, { CCI_REG8(0x464b), 0x30 }, { CCI_REG8(0x4800), 0x04 }, { CCI_REG8(0x4802), 0x02 }, { CCI_REG8(0x480b), 0x10 }, { CCI_REG8(0x480c), 0x80 }, { CCI_REG8(0x480e), 0x04 }, { CCI_REG8(0x480f), 0x32 }, { CCI_REG8(0x481b), 0x12 }, { CCI_REG8(0x4833), 0x30 }, { CCI_REG8(0x4837), 0x08 }, { CCI_REG8(0x484b), 0x27 }, { CCI_REG8(0x4850), 0x42 }, { CCI_REG8(0x4851), 0xaa }, { CCI_REG8(0x4860), 0x01 }, { CCI_REG8(0x4861), 0xec }, { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x4888), 0x00 }, { CCI_REG8(0x4889), 0x03 }, { CCI_REG8(0x488c), 0x60 }, { CCI_REG8(0x4910), 0x28 }, { CCI_REG8(0x4911), 0x01 }, { CCI_REG8(0x4912), 0x0c }, { CCI_REG8(0x491a), 0x40 }, { CCI_REG8(0x4915), 0x00 }, { CCI_REG8(0x4916), 0x0f }, { CCI_REG8(0x4917), 0x00 }, { CCI_REG8(0x4918), 0x07 }, { CCI_REG8(0x4a10), 0x28 }, { CCI_REG8(0x4a11), 0x01 }, { CCI_REG8(0x4a12), 0x0c }, { CCI_REG8(0x4a1a), 0x40 }, { CCI_REG8(0x4a15), 0x00 }, { CCI_REG8(0x4a16), 0x0f }, { CCI_REG8(0x4a17), 0x00 }, { CCI_REG8(0x4a18), 0x07 }, { CCI_REG8(0x4d00), 0x04 }, { CCI_REG8(0x4d01), 0x5a }, { CCI_REG8(0x4d02), 0xbb }, { CCI_REG8(0x4d03), 0x84 }, { CCI_REG8(0x4d04), 0xd1 }, { CCI_REG8(0x4d05), 0x68 }, { CCI_REG8(0xc4fa), 0x10 }, { CCI_REG8(0x3b56), 0x0a }, { CCI_REG8(0x3b57), 0x0a }, { CCI_REG8(0x3b58), 0x0c }, { CCI_REG8(0x3b59), 0x10 }, { CCI_REG8(0x3a1d), 0x30 }, { CCI_REG8(0x3a1e), 0x30 }, { CCI_REG8(0x3a21), 0x30 }, { CCI_REG8(0x3a22), 0x30 }, { CCI_REG8(0x3992), 0x02 }, { CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x39fb), 0x30 }, { CCI_REG8(0x39fc), 0x30 }, { CCI_REG8(0x39fd), 0x30 }, { CCI_REG8(0x39fe), 0x30 }, { CCI_REG8(0x3a6d), 0x83 }, { CCI_REG8(0x3a5e), 0x83 }, { CCI_REG8(0xc500), 0x12 }, { CCI_REG8(0xc501), 0x12 }, { CCI_REG8(0xc502), 0x12 }, { CCI_REG8(0xc503), 0x12 }, { CCI_REG8(0xc505), 0x12 }, { CCI_REG8(0xc506), 0x12 }, { CCI_REG8(0xc507), 0x12 }, { CCI_REG8(0xc508), 0x12 }, { CCI_REG8(0x3a77), 0x12 }, { CCI_REG8(0x3a73), 0x12 }, { CCI_REG8(0x3a7b), 0x12 }, { CCI_REG8(0x3a7f), 0x12 }, { CCI_REG8(0x3b2e), 0x13 }, { CCI_REG8(0x3b29), 0x13 }, { CCI_REG8(0xc439), 0x13 }, { CCI_REG8(0xc469), 0x13 }, { CCI_REG8(0xc41c), 0x89 }, { CCI_REG8(0x3618), 0x80 }, { CCI_REG8(0xc514), 0x51 }, { CCI_REG8(0xc515), 0x2c }, { CCI_REG8(0xc516), 0x16 }, { CCI_REG8(0xc517), 0x0d }, { CCI_REG8(0x3615), 0x7f }, { CCI_REG8(0x3632), 0x99 }, { CCI_REG8(0x3642), 0x00 }, { CCI_REG8(0x3645), 0x80 }, { CCI_REG8(0x3702), 0x2a }, { CCI_REG8(0x3703), 0x2a }, { CCI_REG8(0x3708), 0x2f }, { CCI_REG8(0x3721), 0x15 }, { CCI_REG8(0x3744), 0x28 }, { CCI_REG8(0x3991), 0x0c }, { CCI_REG8(0x371d), 0x24 }, { CCI_REG8(0x371f), 0x0c }, { CCI_REG8(0x374b), 0x03 }, { CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x391d), 0x55 }, { CCI_REG8(0x391e), 0x52 }, { CCI_REG8(0x399d), 0x0c }, { CCI_REG8(0x3a2f), 0x01 }, { CCI_REG8(0x3a30), 0x01 }, { CCI_REG8(0x3a31), 0x01 }, { CCI_REG8(0x3a32), 0x01 }, { CCI_REG8(0x3a34), 0x01 }, { CCI_REG8(0x3a35), 0x01 }, { CCI_REG8(0x3a36), 0x01 }, { CCI_REG8(0x3a37), 0x01 }, { CCI_REG8(0x3a43), 0x01 }, { CCI_REG8(0x3a44), 0x01 }, { CCI_REG8(0x3a45), 0x01 }, { CCI_REG8(0x3a46), 0x01 }, { CCI_REG8(0x3a48), 0x01 }, { CCI_REG8(0x3a49), 0x01 }, { CCI_REG8(0x3a4a), 0x01 }, { CCI_REG8(0x3a4b), 0x01 }, { CCI_REG8(0x3a50), 0x14 }, { CCI_REG8(0x3a54), 0x14 }, { CCI_REG8(0x3a60), 0x20 }, { CCI_REG8(0x3a6f), 0x20 }, { CCI_REG8(0x3ac5), 0x01 }, { CCI_REG8(0x3ac6), 0x01 }, { CCI_REG8(0x3ac7), 0x01 }, { CCI_REG8(0x3ac8), 0x01 }, { CCI_REG8(0x3ac9), 0x01 }, { CCI_REG8(0x3aca), 0x01 }, { CCI_REG8(0x3acb), 0x01 }, { CCI_REG8(0x3acc), 0x01 }, { CCI_REG8(0x3acd), 0x01 }, { CCI_REG8(0x3ace), 0x01 }, { CCI_REG8(0x3acf), 0x01 }, { CCI_REG8(0x3ad0), 0x01 }, { CCI_REG8(0x3ad1), 0x01 }, { CCI_REG8(0x3ad2), 0x01 }, { CCI_REG8(0x3ad3), 0x01 }, { CCI_REG8(0x3ad4), 0x01 }, { CCI_REG8(0x3add), 0x1f }, { CCI_REG8(0x3adf), 0x24 }, { CCI_REG8(0x3aef), 0x1f }, { CCI_REG8(0x3af0), 0x24 }, { CCI_REG8(0x3b92), 0x08 }, { CCI_REG8(0x3b93), 0x08 }, { CCI_REG8(0x3b94), 0x08 }, { CCI_REG8(0x3b95), 0x08 }, { CCI_REG8(0x3be7), 0x1e }, { CCI_REG8(0x3be8), 0x26 }, { CCI_REG8(0xc44a), 0x20 }, { CCI_REG8(0xc44c), 0x20 }, { CCI_REG8(0xc483), 0x00 }, { CCI_REG8(0xc484), 0x00 }, { CCI_REG8(0xc485), 0x00 }, { CCI_REG8(0xc486), 0x00 }, { CCI_REG8(0xc487), 0x01 }, { CCI_REG8(0xc488), 0x01 }, { CCI_REG8(0xc489), 0x01 }, { CCI_REG8(0xc48a), 0x01 }, { CCI_REG8(0xc4c1), 0x00 }, { CCI_REG8(0xc4c2), 0x00 }, { CCI_REG8(0xc4c3), 0x00 }, { CCI_REG8(0xc4c4), 0x00 }, { CCI_REG8(0xc4c6), 0x10 }, { CCI_REG8(0xc4c7), 0x10 }, { CCI_REG8(0xc4c8), 0x10 }, { CCI_REG8(0xc4c9), 0x10 }, { CCI_REG8(0xc4ca), 0x10 }, { CCI_REG8(0xc4cb), 0x10 }, { CCI_REG8(0xc4cc), 0x10 }, { CCI_REG8(0xc4cd), 0x10 }, { CCI_REG8(0xc4ea), 0x07 }, { CCI_REG8(0xc4eb), 0x07 }, { CCI_REG8(0xc4ec), 0x07 }, { CCI_REG8(0xc4ed), 0x07 }, { CCI_REG8(0xc4ee), 0x07 }, { CCI_REG8(0xc4f6), 0x10 }, { CCI_REG8(0xc4f7), 0x10 }, { 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CCI_REG8(0x3b89), 0xcd }, { CCI_REG8(0x3b8a), 0xcd }, { CCI_REG8(0x3b8b), 0xcd }, { CCI_REG8(0x3b8c), 0xcd }, { CCI_REG8(0x3b8d), 0xcd }, { CCI_REG8(0x3b8e), 0xcd }, { CCI_REG8(0x3b8f), 0xcd }, { CCI_REG8(0x3b90), 0xcd }, { CCI_REG8(0x3b91), 0xcd }, { CCI_REG8(0x3b92), 0xcd }, { CCI_REG8(0x3b93), 0xcd }, { CCI_REG8(0x3b94), 0xcd }, { CCI_REG8(0x3b95), 0xcd }, { CCI_REG8(0x3b96), 0xcd }, { CCI_REG8(0x3b97), 0xcd }, { CCI_REG8(0x3b98), 0xcd }, { CCI_REG8(0x3b99), 0xcd }, { CCI_REG8(0x3b9a), 0xcd }, { CCI_REG8(0x3b9b), 0xcd }, { CCI_REG8(0x3b9c), 0xcd }, { CCI_REG8(0x3b9d), 0xcd }, { CCI_REG8(0x3b9e), 0xcd }, { CCI_REG8(0x3b9f), 0xcd }, { CCI_REG8(0x3ba0), 0xcd }, { CCI_REG8(0x3ba1), 0xcd }, { CCI_REG8(0x3ba2), 0xcd }, { CCI_REG8(0x3ba3), 0xcd }, { CCI_REG8(0x3ba4), 0xcd }, { CCI_REG8(0x3ba5), 0xcd }, { CCI_REG8(0x3ba6), 0xcd }, { CCI_REG8(0x3ba7), 0xcd }, { CCI_REG8(0x3ba8), 0xcd }, { CCI_REG8(0x3ba9), 0xcd }, { CCI_REG8(0x3baa), 0xcd }, { CCI_REG8(0x3bab), 0xcd }, { CCI_REG8(0x3bac), 0xcd }, { CCI_REG8(0x3bad), 0xcd }, { CCI_REG8(0x3bae), 0xcd }, { CCI_REG8(0x3baf), 0xcd }, { CCI_REG8(0x3bb0), 0xcd }, { CCI_REG8(0x3bb1), 0xcd }, { CCI_REG8(0x3bb2), 0xcd }, { CCI_REG8(0x3bb3), 0xcd }, { CCI_REG8(0x3bb4), 0xcd }, { CCI_REG8(0x3bb5), 0xcd }, { CCI_REG8(0x3bb6), 0xcd }, { CCI_REG8(0x3bb7), 0xcd }, { CCI_REG8(0x3bb8), 0xcd }, { CCI_REG8(0x3bb9), 0xcd }, { CCI_REG8(0x3bba), 0xcd }, { CCI_REG8(0x3bbb), 0xcd }, { CCI_REG8(0x3bbc), 0xcd }, { CCI_REG8(0x3bbd), 0xcd }, { CCI_REG8(0x3bbe), 0xcd }, { CCI_REG8(0x3bbf), 0xcd }, { CCI_REG8(0x3bc0), 0xcd }, { CCI_REG8(0x3bc1), 0xcd }, { CCI_REG8(0x3bc2), 0xcd }, { CCI_REG8(0x3bc3), 0xcd }, { CCI_REG8(0x3bc4), 0xcd }, { CCI_REG8(0x3bc5), 0xcd }, { CCI_REG8(0x3bc6), 0xcd }, { CCI_REG8(0x3bc7), 0xcd }, { CCI_REG8(0x3bc8), 0xcd }, { CCI_REG8(0x3bc9), 0xcd }, { CCI_REG8(0x3bca), 0xcd }, { CCI_REG8(0x3bcb), 0xcd }, { CCI_REG8(0x3bcc), 0xcd }, { CCI_REG8(0x3bcd), 0xcd }, { CCI_REG8(0x3bce), 0xcd }, { CCI_REG8(0x3bcf), 0xcd }, { CCI_REG8(0x3bd0), 0xcd }, { CCI_REG8(0x3bd1), 0xcd }, { CCI_REG8(0x3bd2), 0xcd }, { CCI_REG8(0x3bd3), 0xcd }, { CCI_REG8(0x3bd4), 0xcd }, { CCI_REG8(0x3bd5), 0xcd }, { CCI_REG8(0x3bd6), 0xcd }, { CCI_REG8(0x3bd7), 0xcd }, { CCI_REG8(0x3bd8), 0xcd }, { CCI_REG8(0x3bd9), 0xcd }, { CCI_REG8(0x3bda), 0xcd }, { CCI_REG8(0x3bdb), 0xcd }, { CCI_REG8(0x3bdc), 0xcd }, { CCI_REG8(0x3bdd), 0xcd }, { CCI_REG8(0x3bde), 0xcd }, { CCI_REG8(0x3bdf), 0xcd }, { CCI_REG8(0x3be0), 0xcd }, { CCI_REG8(0x3be1), 0xcd }, { CCI_REG8(0x3be2), 0xcd }, { CCI_REG8(0x3be3), 0xcd }, { CCI_REG8(0x3be4), 0xcd }, { CCI_REG8(0x3be5), 0xcd }, { CCI_REG8(0x3be6), 0xcd }, { CCI_REG8(0x3be7), 0xcd }, { CCI_REG8(0x3be8), 0xcd }, { CCI_REG8(0x3be9), 0xcd }, { CCI_REG8(0x3bea), 0xcd }, { CCI_REG8(0x3beb), 0xcd }, { CCI_REG8(0x3bec), 0xcd }, { CCI_REG8(0x3bed), 0xcd }, { CCI_REG8(0x3bee), 0xcd }, { CCI_REG8(0x3bef), 0xcd }, { CCI_REG8(0x3bf0), 0xcd }, { CCI_REG8(0x3bf1), 0xcd }, { CCI_REG8(0x3bf2), 0xcd }, { CCI_REG8(0x3bf3), 0xcd }, { CCI_REG8(0x3bf4), 0xcd }, { CCI_REG8(0x3bf5), 0xcd }, { CCI_REG8(0x3bf6), 0xcd }, { CCI_REG8(0x3bf7), 0xcd }, { CCI_REG8(0x3bf8), 0xcd }, { CCI_REG8(0x3bf9), 0xcd }, { CCI_REG8(0x3bfa), 0xcd }, { CCI_REG8(0x3bfb), 0xcd }, { CCI_REG8(0x3bfc), 0xcd }, { CCI_REG8(0x3bfd), 0xcd }, { CCI_REG8(0x3bfe), 0xcd }, { CCI_REG8(0x3bff), 0xcd }, { CCI_REG8(0x3c00), 0xcd }, { CCI_REG8(0x3c01), 0xcd }, { CCI_REG8(0x3c02), 0xcd }, { CCI_REG8(0x3c03), 0xcd }, { CCI_REG8(0x3c04), 0xcd }, { CCI_REG8(0x3c05), 0xcd }, { CCI_REG8(0x3c06), 0xcd }, { CCI_REG8(0x3c07), 0xcd }, { CCI_REG8(0x3c08), 0xcd }, { CCI_REG8(0x3c09), 0xcd }, { CCI_REG8(0x3c0a), 0xcd }, { CCI_REG8(0x3c0b), 0xcd }, { CCI_REG8(0x3c0c), 0xcd }, { CCI_REG8(0x3c0d), 0xcd }, { CCI_REG8(0x3c0e), 0xcd }, { CCI_REG8(0x3c0f), 0xcd }, { CCI_REG8(0x3c10), 0xcd }, { CCI_REG8(0x3c11), 0xcd }, { CCI_REG8(0x3c12), 0xcd }, { CCI_REG8(0x3c13), 0xcd }, { CCI_REG8(0x3c14), 0xcd }, { CCI_REG8(0x3c15), 0xcd }, { CCI_REG8(0x3c16), 0xcd }, { CCI_REG8(0x3c17), 0xcd }, { CCI_REG8(0x3c18), 0xcd }, { CCI_REG8(0x3c19), 0xcd }, { CCI_REG8(0x3c1a), 0xcd }, { CCI_REG8(0x3c1b), 0xcd }, { CCI_REG8(0x3c1c), 0xcd }, { CCI_REG8(0x3c1d), 0xcd }, { CCI_REG8(0x3c1e), 0xcd }, { CCI_REG8(0x3c1f), 0xcd }, { CCI_REG8(0x3c20), 0xcd }, { CCI_REG8(0x3c21), 0xcd }, { CCI_REG8(0x3c22), 0xcd }, { CCI_REG8(0x3c23), 0xcd }, { CCI_REG8(0x3c24), 0xcd }, { CCI_REG8(0x3c25), 0xcd }, { CCI_REG8(0x3c26), 0xcd }, { CCI_REG8(0x3c27), 0xcd }, { CCI_REG8(0x3c28), 0xcd }, { CCI_REG8(0x3c29), 0xcd }, { CCI_REG8(0x3c2a), 0xcd }, { CCI_REG8(0x3c2b), 0xcd }, { CCI_REG8(0x3c2c), 0xcd }, { CCI_REG8(0x3c2d), 0xcd }, { CCI_REG8(0x3c2e), 0xcd }, { CCI_REG8(0x3c2f), 0xcd }, { CCI_REG8(0x3c30), 0xcd }, { CCI_REG8(0x3c31), 0xcd }, { CCI_REG8(0x3c32), 0xcd }, { CCI_REG8(0x3c33), 0xcd }, { CCI_REG8(0x3c34), 0xcd }, { CCI_REG8(0x3c35), 0xcd }, { CCI_REG8(0x3c36), 0xcd }, { CCI_REG8(0x3c37), 0xcd }, { CCI_REG8(0x3c38), 0xcd }, { CCI_REG8(0x3c39), 0xcd }, { CCI_REG8(0x3c3a), 0xcd }, { CCI_REG8(0x3c3b), 0xcd }, { CCI_REG8(0x3c3c), 0xcd }, { CCI_REG8(0x3c3d), 0xcd }, { CCI_REG8(0x3c3e), 0xcd }, { CCI_REG8(0x3c3f), 0xcd }, { CCI_REG8(0x3c40), 0xcd }, { CCI_REG8(0x3c41), 0xcd }, { CCI_REG8(0x3c42), 0xcd }, { CCI_REG8(0x3c43), 0xcd }, { CCI_REG8(0x3c44), 0xcd }, { CCI_REG8(0x3c45), 0xcd }, { CCI_REG8(0x3c46), 0xcd }, { CCI_REG8(0x3c47), 0xcd }, { CCI_REG8(0x3c48), 0xcd }, { CCI_REG8(0x3c49), 0xcd }, { CCI_REG8(0x3c4a), 0xcd }, { CCI_REG8(0x3c4b), 0xcd }, { CCI_REG8(0x3c4c), 0xcd }, { CCI_REG8(0x3c4d), 0xcd }, { CCI_REG8(0x3c4e), 0xcd }, { CCI_REG8(0x3c4f), 0xcd }, { CCI_REG8(0x3c50), 0xcd }, { CCI_REG8(0x3c51), 0xcd }, { CCI_REG8(0x3c52), 0xcd }, { CCI_REG8(0x3c53), 0xcd }, { CCI_REG8(0x3c54), 0xcd }, { CCI_REG8(0x3c55), 0xcd }, { CCI_REG8(0x3c56), 0xcd }, { CCI_REG8(0x3c57), 0xcd }, { CCI_REG8(0x3c58), 0xcd }, { CCI_REG8(0x3c59), 0xcd }, { CCI_REG8(0x3c5a), 0xcd }, { CCI_REG8(0x3c5b), 0xcd }, { CCI_REG8(0x3c5c), 0xcd }, { CCI_REG8(0x3c5d), 0xcd }, { CCI_REG8(0x3c5e), 0xcd }, { CCI_REG8(0x3c5f), 0xcd }, { CCI_REG8(0x3c60), 0xcd }, { CCI_REG8(0x3c61), 0xcd }, { CCI_REG8(0x3c62), 0xcd }, { CCI_REG8(0x3c63), 0xcd }, { CCI_REG8(0x3c64), 0xcd }, { CCI_REG8(0x3c65), 0xcd }, { CCI_REG8(0x3c66), 0xcd }, { CCI_REG8(0x3c67), 0xcd }, { CCI_REG8(0x3c68), 0xcd }, { CCI_REG8(0x3c69), 0xcd }, { CCI_REG8(0x3c6a), 0xcd }, { CCI_REG8(0x3c6b), 0xcd }, { CCI_REG8(0x3c6c), 0xcd }, { CCI_REG8(0x3c6d), 0xcd }, { CCI_REG8(0x3c6e), 0xcd }, { CCI_REG8(0x3c6f), 0xcd }, { CCI_REG8(0x3c70), 0xcd }, { CCI_REG8(0x3c71), 0xcd }, { CCI_REG8(0x3c72), 0xcd }, { CCI_REG8(0x3c73), 0xcd }, { CCI_REG8(0x3c74), 0xcd }, { CCI_REG8(0x3c75), 0xcd }, { CCI_REG8(0x3c76), 0xcd }, { CCI_REG8(0x3c77), 0xcd }, { CCI_REG8(0x3c78), 0xcd }, { CCI_REG8(0x3c79), 0xcd }, { CCI_REG8(0x3c7a), 0xcd }, { CCI_REG8(0x3c7b), 0xcd }, { CCI_REG8(0x3c7c), 0xcd }, { CCI_REG8(0x3c7d), 0xcd }, { CCI_REG8(0x3c7e), 0xcd }, { CCI_REG8(0x3c7f), 0xcd }, { CCI_REG8(0x3c80), 0xcd }, { CCI_REG8(0x3c81), 0xcd }, { CCI_REG8(0x3c82), 0xcd }, { CCI_REG8(0x3c83), 0xcd }, { CCI_REG8(0x3c84), 0xcd }, { CCI_REG8(0x3c85), 0xcd }, { CCI_REG8(0x3c86), 0xcd }, { CCI_REG8(0x3c87), 0xcd }, { CCI_REG8(0x3c88), 0xcd }, { CCI_REG8(0x3c89), 0xcd }, { CCI_REG8(0x3c8a), 0xcd }, { CCI_REG8(0x3c8b), 0xcd }, { CCI_REG8(0x3c8c), 0xcd }, { CCI_REG8(0x3c8d), 0xcd }, { CCI_REG8(0x3c8e), 0xcd }, { CCI_REG8(0x3c8f), 0xcd }, { CCI_REG8(0x3c90), 0xcd }, { CCI_REG8(0x3c91), 0xcd }, { CCI_REG8(0x3c92), 0xcd }, { CCI_REG8(0x3c93), 0xcd }, { CCI_REG8(0x3c94), 0xcd }, { CCI_REG8(0x3c95), 0xcd }, { CCI_REG8(0x3c96), 0xcd }, { CCI_REG8(0x3c97), 0xcd }, { CCI_REG8(0x3c98), 0xcd }, { CCI_REG8(0x3c99), 0xcd }, { CCI_REG8(0x3c9a), 0xcd }, { CCI_REG8(0x3c9b), 0xcd }, { CCI_REG8(0x3c9c), 0xcd }, { CCI_REG8(0x3c9d), 0xcd }, { CCI_REG8(0x3c9e), 0xcd }, { CCI_REG8(0x3c9f), 0xcd }, { CCI_REG8(0x3ca0), 0xcd }, { CCI_REG8(0x3ca1), 0xcd }, { CCI_REG8(0x3ca2), 0xcd }, { CCI_REG8(0x3ca3), 0xcd }, { CCI_REG8(0x3ca4), 0xcd }, { CCI_REG8(0x3ca5), 0xcd }, { CCI_REG8(0x3ca6), 0xcd }, { CCI_REG8(0x3ca7), 0xcd }, { CCI_REG8(0x3ca8), 0xcd }, { CCI_REG8(0x3ca9), 0xcd }, { CCI_REG8(0x3caa), 0xcd }, { CCI_REG8(0x3cab), 0xcd }, { CCI_REG8(0x3cac), 0xcd }, { CCI_REG8(0x3cad), 0xcd }, { CCI_REG8(0x3cae), 0xcd }, { CCI_REG8(0x3caf), 0xcd }, { CCI_REG8(0x3cb0), 0xcd }, { CCI_REG8(0x3cb1), 0x40 }, { CCI_REG8(0x3cb2), 0x40 }, { CCI_REG8(0x3cb3), 0x40 }, { CCI_REG8(0x3cb4), 0x40 }, { CCI_REG8(0x3cb5), 0x40 }, { CCI_REG8(0x3cb6), 0x40 }, { CCI_REG8(0x3cb7), 0x40 }, { CCI_REG8(0x3cb8), 0x40 }, { CCI_REG8(0x3cb9), 0x40 }, { CCI_REG8(0x3cba), 0x40 }, { CCI_REG8(0x3cbb), 0x40 }, { CCI_REG8(0x3cbc), 0x40 }, { CCI_REG8(0x3cbd), 0x40 }, { CCI_REG8(0x3cbe), 0x40 }, { CCI_REG8(0x3cbf), 0x40 }, { CCI_REG8(0x3cc0), 0x40 }, { CCI_REG8(0x3cc1), 0x40 }, { CCI_REG8(0x3cc2), 0x40 }, { CCI_REG8(0x3cc3), 0x40 }, { CCI_REG8(0x3cc4), 0x40 }, { CCI_REG8(0x3cc5), 0x40 }, { CCI_REG8(0x3cc6), 0x40 }, { CCI_REG8(0x3cc7), 0x40 }, { CCI_REG8(0x3cc8), 0x40 }, { CCI_REG8(0x3cc9), 0x40 }, { CCI_REG8(0x3cca), 0x40 }, { CCI_REG8(0x3ccb), 0x40 }, { CCI_REG8(0x3ccc), 0x40 }, { CCI_REG8(0x3ccd), 0x40 }, { CCI_REG8(0x3cce), 0x40 }, { CCI_REG8(0x3ccf), 0x40 }, { CCI_REG8(0x3cd0), 0x40 }, { CCI_REG8(0x3cd1), 0x40 }, { CCI_REG8(0x3cd2), 0x40 }, { CCI_REG8(0x3cd3), 0x40 }, { CCI_REG8(0x3cd4), 0x40 }, { CCI_REG8(0x3cd5), 0x40 }, { CCI_REG8(0x3cd6), 0x40 }, { CCI_REG8(0x3cd7), 0x40 }, { CCI_REG8(0x3cd8), 0x40 }, { CCI_REG8(0x3cd9), 0x40 }, { CCI_REG8(0x3cda), 0x40 }, { CCI_REG8(0x3cdb), 0x40 }, { CCI_REG8(0x3cdc), 0x40 }, { CCI_REG8(0x3cdd), 0x40 }, { CCI_REG8(0x3cde), 0x40 }, { CCI_REG8(0x3cdf), 0x40 }, { CCI_REG8(0x3ce0), 0x40 }, { CCI_REG8(0x3ce1), 0x40 }, { CCI_REG8(0x3ce2), 0x40 }, { CCI_REG8(0x3ce3), 0x40 }, { CCI_REG8(0x3ce4), 0x40 }, { CCI_REG8(0x3ce5), 0x40 }, { CCI_REG8(0x3ce6), 0x40 }, { CCI_REG8(0x3ce7), 0x40 }, { CCI_REG8(0x3ce8), 0x40 }, { CCI_REG8(0x3ce9), 0x40 }, { CCI_REG8(0x3cea), 0x40 }, { CCI_REG8(0x3ceb), 0x40 }, { CCI_REG8(0x3cec), 0x40 }, { CCI_REG8(0x3ced), 0x40 }, { CCI_REG8(0x3cee), 0x40 }, { CCI_REG8(0x3cef), 0x40 }, { CCI_REG8(0x3cf0), 0x40 }, { CCI_REG8(0x3cf1), 0x40 }, { CCI_REG8(0x3cf2), 0x40 }, { CCI_REG8(0x3cf3), 0x40 }, { CCI_REG8(0x3cf4), 0x40 }, { CCI_REG8(0x3cf5), 0x40 }, { CCI_REG8(0x3cf6), 0x40 }, { CCI_REG8(0x3cf7), 0x40 }, { CCI_REG8(0x3cf8), 0x40 }, { CCI_REG8(0x3cf9), 0x40 }, { CCI_REG8(0x3cfa), 0x40 }, { CCI_REG8(0x3cfb), 0x40 }, { CCI_REG8(0x3cfc), 0x40 }, { CCI_REG8(0x3cfd), 0x40 }, { CCI_REG8(0x3cfe), 0x40 }, { CCI_REG8(0x3cff), 0x40 }, { CCI_REG8(0x3d00), 0x40 }, { CCI_REG8(0x3d01), 0x40 }, { CCI_REG8(0x3d02), 0x40 }, { CCI_REG8(0x3d03), 0x40 }, { CCI_REG8(0x3d04), 0x40 }, { CCI_REG8(0x3d05), 0x40 }, { CCI_REG8(0x3d06), 0x40 }, { CCI_REG8(0x3d07), 0x40 }, { CCI_REG8(0x3d08), 0x40 }, { CCI_REG8(0x3d09), 0x40 }, { CCI_REG8(0x3d0a), 0x40 }, { CCI_REG8(0x3d0b), 0xcd }, { CCI_REG8(0x3d0c), 0xcd }, { CCI_REG8(0x3d0d), 0xcd }, { CCI_REG8(0x3d0e), 0xcd }, { CCI_REG8(0x3d0f), 0xcd }, { CCI_REG8(0x3d10), 0xcd }, { CCI_REG8(0x3d11), 0xcd }, { CCI_REG8(0x3d12), 0xcd }, { CCI_REG8(0x3d13), 0xcd }, { CCI_REG8(0x3d14), 0xcd }, { CCI_REG8(0x3d15), 0xcd }, { CCI_REG8(0x3d16), 0xcd }, { CCI_REG8(0x3d17), 0xcd }, { CCI_REG8(0x3d18), 0xcd }, { CCI_REG8(0x3d19), 0xcd }, { CCI_REG8(0x3d1a), 0xcd }, { CCI_REG8(0x3d1b), 0xcd }, { CCI_REG8(0x3d1c), 0xcd }, { CCI_REG8(0x3d1d), 0xcd }, { CCI_REG8(0x3d1e), 0xcd }, { CCI_REG8(0x3d1f), 0xcd }, { CCI_REG8(0x3d20), 0xcd }, { CCI_REG8(0x3d21), 0xcd }, { CCI_REG8(0x3d22), 0xcd }, { CCI_REG8(0x3d23), 0xcd }, { CCI_REG8(0x3d24), 0xcd }, { CCI_REG8(0x3d25), 0xcd }, { CCI_REG8(0x3d26), 0xcd }, { CCI_REG8(0x3d27), 0xcd }, { CCI_REG8(0x3d28), 0xcd }, { CCI_REG8(0x3d29), 0xcd }, { CCI_REG8(0x3d2a), 0xcd }, { CCI_REG8(0x3d2b), 0xcd }, { CCI_REG8(0x3d2c), 0xcd }, { CCI_REG8(0x3d2d), 0xcd }, { CCI_REG8(0x3d2e), 0xcd }, { CCI_REG8(0x3d2f), 0xcd }, { CCI_REG8(0x3d30), 0xcd }, { CCI_REG8(0x3d31), 0xcd }, { CCI_REG8(0x3d32), 0xcd }, { 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CCI_REG8(0x3dc1), 0xcd }, { CCI_REG8(0x3dc2), 0xcd }, { CCI_REG8(0x3dc3), 0xcd }, { CCI_REG8(0x3dc4), 0xcd }, { CCI_REG8(0x3dc5), 0xcd }, { CCI_REG8(0x3dc6), 0xcd }, { CCI_REG8(0x3dc7), 0xcd }, { CCI_REG8(0x3dc8), 0xcd }, { CCI_REG8(0x3dc9), 0xcd }, { CCI_REG8(0x3dca), 0xcd }, { CCI_REG8(0x3dcb), 0xcd }, { CCI_REG8(0x3dcc), 0xcd }, { CCI_REG8(0x3dcd), 0xcd }, { CCI_REG8(0x3dce), 0xcd }, { CCI_REG8(0x3dcf), 0xcd }, { CCI_REG8(0x3dd0), 0xcd }, { CCI_REG8(0x3dd1), 0xcd }, { CCI_REG8(0x3dd2), 0xcd }, { CCI_REG8(0x3dd3), 0xcd }, { CCI_REG8(0x3dd4), 0xcd }, { CCI_REG8(0x3dd5), 0xcd }, { CCI_REG8(0x3dd6), 0xcd }, { CCI_REG8(0x3dd7), 0xcd }, { CCI_REG8(0x3dd8), 0xcd }, { CCI_REG8(0x3dd9), 0xcd }, { CCI_REG8(0x3dda), 0xcd }, { CCI_REG8(0x3ddb), 0xcd }, { CCI_REG8(0x3ddc), 0xcd }, { CCI_REG8(0x3ddd), 0xcd }, { CCI_REG8(0x3dde), 0xcd }, { CCI_REG8(0x3ddf), 0xcd }, { CCI_REG8(0x3de0), 0xcd }, { CCI_REG8(0x3de1), 0xcd }, { CCI_REG8(0x3de2), 0xcd }, { CCI_REG8(0x3de3), 0xcd }, { CCI_REG8(0x3de4), 0xcd }, { CCI_REG8(0x3de5), 0xcd }, { CCI_REG8(0x3de6), 0xcd }, { CCI_REG8(0x3de7), 0xcd }, { CCI_REG8(0x3de8), 0xcd }, { CCI_REG8(0x3de9), 0xcd }, { CCI_REG8(0x3dea), 0xcd }, { CCI_REG8(0x3deb), 0xcd }, { CCI_REG8(0x3dec), 0xcd }, { CCI_REG8(0x3ded), 0xcd }, { CCI_REG8(0x3dee), 0xcd }, { CCI_REG8(0x3def), 0xcd }, { CCI_REG8(0x3df0), 0xcd }, { CCI_REG8(0x3df1), 0xcd }, { CCI_REG8(0x3df2), 0xcd }, { CCI_REG8(0x3df3), 0xcd }, { CCI_REG8(0x3df4), 0xcd }, { CCI_REG8(0x3df5), 0xcd }, { CCI_REG8(0x3df6), 0xcd }, { CCI_REG8(0x3df7), 0xcd }, { CCI_REG8(0x3df8), 0xcd }, { CCI_REG8(0x3df9), 0xcd }, { CCI_REG8(0x3dfa), 0xcd }, { CCI_REG8(0x3dfb), 0xcd }, { CCI_REG8(0x3dfc), 0xcd }, { CCI_REG8(0x3dfd), 0xcd }, { CCI_REG8(0x3dfe), 0xcd }, { CCI_REG8(0x3dff), 0xcd }, { CCI_REG8(0x3e00), 0xcd }, { CCI_REG8(0x3e01), 0xcd }, { CCI_REG8(0x3e02), 0xcd }, { CCI_REG8(0x3e03), 0xcd }, { CCI_REG8(0x3e04), 0xcd }, { CCI_REG8(0x3e05), 0xcd }, { CCI_REG8(0x3e06), 0xcd }, { CCI_REG8(0x3e07), 0xcd }, { CCI_REG8(0x3e08), 0xcd }, { CCI_REG8(0x3e09), 0xcd }, { CCI_REG8(0x3e0a), 0xcd }, { CCI_REG8(0x3e0b), 0xcd }, { CCI_REG8(0x3e0c), 0xcd }, { CCI_REG8(0x3e0d), 0xcd }, { CCI_REG8(0x3e0e), 0xcd }, { CCI_REG8(0x3e0f), 0xcd }, { CCI_REG8(0x3e10), 0xcd }, { CCI_REG8(0x3e11), 0xcd }, { CCI_REG8(0x3e12), 0xcd }, { CCI_REG8(0x3e13), 0xcd }, { CCI_REG8(0x3e14), 0xcd }, { CCI_REG8(0x3e15), 0xcd }, { CCI_REG8(0x3e16), 0xcd }, { CCI_REG8(0x3e17), 0xcd }, { CCI_REG8(0x3e18), 0xcd }, { CCI_REG8(0x3e19), 0xcd }, { CCI_REG8(0x3e1a), 0xcd }, { CCI_REG8(0x3e1b), 0xcd }, { CCI_REG8(0x3e1c), 0xcd }, { CCI_REG8(0x3e1d), 0xcd }, { CCI_REG8(0x3e1e), 0xcd }, { CCI_REG8(0x3e1f), 0xcd }, { CCI_REG8(0x3e20), 0xcd }, { CCI_REG8(0x3e21), 0xcd }, { CCI_REG8(0x3e22), 0xcd }, { CCI_REG8(0x3e23), 0xcd }, { CCI_REG8(0x3e24), 0xcd }, { CCI_REG8(0x3e25), 0xcd }, { CCI_REG8(0x3e26), 0xcd }, { CCI_REG8(0x3e27), 0xcd }, { CCI_REG8(0x3e28), 0xcd }, { CCI_REG8(0x3e29), 0xcd }, { CCI_REG8(0x3e2a), 0xcd }, { CCI_REG8(0x3e2b), 0xcd }, { CCI_REG8(0x3e2c), 0xcd }, { CCI_REG8(0x3e2d), 0xcd }, { CCI_REG8(0x3e2e), 0xcd }, { CCI_REG8(0x3e2f), 0xcd }, { CCI_REG8(0x3e30), 0xcd }, { CCI_REG8(0x3e31), 0xcd }, { CCI_REG8(0x3e32), 0xcd }, { CCI_REG8(0x3e33), 0xcd }, { CCI_REG8(0x3e34), 0xcd }, { CCI_REG8(0x3e35), 0xcd }, { CCI_REG8(0x3e36), 0xcd }, { CCI_REG8(0x3e37), 0xcd }, { CCI_REG8(0x3e38), 0xcd }, { CCI_REG8(0x3e39), 0xcd }, { CCI_REG8(0x3e3a), 0xcd }, { CCI_REG8(0x3e3b), 0xcd }, { CCI_REG8(0x3e3c), 0xcd }, { CCI_REG8(0x3e3d), 0xcd }, { CCI_REG8(0x3e3e), 0xcd }, { CCI_REG8(0x3e3f), 0xcd }, { CCI_REG8(0x3e40), 0xcd }, { CCI_REG8(0x3e41), 0xcd }, { CCI_REG8(0x3e42), 0xcd }, { CCI_REG8(0x3e43), 0xcd }, { CCI_REG8(0x3e44), 0xcd }, { CCI_REG8(0x3e45), 0xcd }, { CCI_REG8(0x3e46), 0xcd }, { CCI_REG8(0x3e47), 0xcd }, { CCI_REG8(0x3e48), 0xcd }, { CCI_REG8(0x3e49), 0xcd }, { CCI_REG8(0x3e4a), 0xcd }, { CCI_REG8(0x3e4b), 0xcd }, { CCI_REG8(0x3e4c), 0xcd }, { CCI_REG8(0x3e4d), 0xcd }, { CCI_REG8(0x3e4e), 0xcd }, { CCI_REG8(0x3e4f), 0xcd }, { CCI_REG8(0x3e50), 0xcd }, { CCI_REG8(0x3e51), 0xcd }, { CCI_REG8(0x3e52), 0xcd }, { CCI_REG8(0x3e53), 0xcd }, { CCI_REG8(0x3e54), 0xcd }, { CCI_REG8(0x3e55), 0xcd }, { CCI_REG8(0x3e56), 0xcd }, { CCI_REG8(0x3e57), 0xcd }, { CCI_REG8(0x3e58), 0xcd }, { CCI_REG8(0x3e59), 0xcd }, { CCI_REG8(0x3e5a), 0xcd }, { CCI_REG8(0x3e5b), 0xcd }, { CCI_REG8(0x3e5c), 0xcd }, { CCI_REG8(0x3e5d), 0xcd }, { CCI_REG8(0x3e5e), 0xcd }, { CCI_REG8(0x3e5f), 0xcd }, { CCI_REG8(0x3e60), 0xcd }, { CCI_REG8(0x3e61), 0xcd }, { CCI_REG8(0x3e62), 0xcd }, { CCI_REG8(0x3e63), 0xcd }, { CCI_REG8(0x3e64), 0xcd }, { CCI_REG8(0x3e65), 0xcd }, { CCI_REG8(0x3e66), 0xcd }, { CCI_REG8(0x3e67), 0xcd }, { CCI_REG8(0x3e68), 0xcd }, { CCI_REG8(0x3e69), 0xcd }, { CCI_REG8(0x3e6a), 0xcd }, { CCI_REG8(0x3e6b), 0xcd }, { CCI_REG8(0x3e6c), 0xcd }, { CCI_REG8(0x3e6d), 0xcd }, { CCI_REG8(0x3e6e), 0xcd }, { CCI_REG8(0x3e6f), 0xcd }, { CCI_REG8(0x3e70), 0xcd }, { CCI_REG8(0x3e71), 0xcd }, { CCI_REG8(0x3e72), 0xcd }, { CCI_REG8(0x3e73), 0xcd }, { CCI_REG8(0x3e74), 0xcd }, { CCI_REG8(0x3e75), 0xcd }, { CCI_REG8(0x3e76), 0xcd }, { CCI_REG8(0x3e77), 0xcd }, { CCI_REG8(0x3e78), 0xcd }, { CCI_REG8(0x3e79), 0xcd }, { CCI_REG8(0x3e7a), 0xcd }, { CCI_REG8(0x3e7b), 0xcd }, { CCI_REG8(0x3e7c), 0xcd }, { CCI_REG8(0x3e7d), 0xcd }, { CCI_REG8(0x3e7e), 0xcd }, { CCI_REG8(0x3e7f), 0xcd }, { CCI_REG8(0x3e80), 0xcd }, { CCI_REG8(0x3e81), 0xcd }, { CCI_REG8(0x3e82), 0xcd }, { CCI_REG8(0x3e83), 0xcd }, { CCI_REG8(0x3e84), 0xcd }, { CCI_REG8(0x3e85), 0xcd }, { CCI_REG8(0x3e86), 0xcd }, { CCI_REG8(0x3e87), 0xcd }, { CCI_REG8(0x3e88), 0xcd }, { CCI_REG8(0x3e89), 0xcd }, { CCI_REG8(0x3e8a), 0xcd }, { CCI_REG8(0x3e8b), 0xcd }, { CCI_REG8(0x3e8c), 0xcd }, { CCI_REG8(0x3e8d), 0xcd }, { CCI_REG8(0x3e8e), 0xcd }, { CCI_REG8(0x3e8f), 0xcd }, { CCI_REG8(0x3e90), 0xcd }, { CCI_REG8(0x3e91), 0xcd }, { CCI_REG8(0x3e92), 0xcd }, { CCI_REG8(0x3e93), 0xcd }, { CCI_REG8(0x3e94), 0xcd }, { CCI_REG8(0x3e95), 0xcd }, { CCI_REG8(0x3e96), 0xcd }, { CCI_REG8(0x3e97), 0xcd }, { CCI_REG8(0x3e98), 0xcd }, { CCI_REG8(0x3e99), 0xcd }, { CCI_REG8(0x3e9a), 0xcd }, { CCI_REG8(0x3e9b), 0xcd }, { CCI_REG8(0x3e9c), 0xcd }, { CCI_REG8(0x3e9d), 0xcd }, { CCI_REG8(0x3e9e), 0xcd }, { CCI_REG8(0x3e9f), 0xcd }, { CCI_REG8(0xfff9), 0x06 }, { CCI_REG8(0xc03f), 0x01 }, { CCI_REG8(0xc03e), 0x08 }, { CCI_REG8(0xc02c), 0xff }, { CCI_REG8(0xc005), 0x06 }, { CCI_REG8(0xc006), 0x30 }, { CCI_REG8(0xc007), 0xc0 }, { CCI_REG8(0xc027), 0x01 }, { CCI_REG8(0x30c0), 0x05 }, { CCI_REG8(0x30c1), 0x9f }, { CCI_REG8(0x30c2), 0x06 }, { CCI_REG8(0x30c3), 0x5f }, { CCI_REG8(0x30c4), 0x80 }, { CCI_REG8(0x30c5), 0x08 }, { CCI_REG8(0x30c6), 0x39 }, { CCI_REG8(0x30c7), 0x00 }, { CCI_REG8(0xc046), 0x20 }, { CCI_REG8(0xc043), 0x01 }, { CCI_REG8(0xc04b), 0x01 }, { CCI_REG8(0x0102), 0x01 }, { CCI_REG8(0x0100), 0x00 }, { CCI_REG8(0x0102), 0x00 }, { CCI_REG8(0x3015), 0xf0 }, { CCI_REG8(0x3018), 0xf0 }, { CCI_REG8(0x301c), 0xf0 }, { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 } }; static const struct cci_reg_sequence ov64a40_9248x6944[] = { { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 } }; static const struct cci_reg_sequence ov64a40_8000x6000[] = { { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 } }; static const struct cci_reg_sequence ov64a40_4624_3472[] = { { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x50 }, { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x08 }, { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0xba }, { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x08 }, { CCI_REG8(0x3857), 0x08 }, { CCI_REG8(0x3858), 0x10 }, { CCI_REG8(0x3859), 0x10 }, { CCI_REG8(0x4016), 0x0f }, { CCI_REG8(0x4018), 0x03 }, { CCI_REG8(0x4504), 0x1e }, { CCI_REG8(0x4523), 0x41 }, { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x12 }, { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a60), 0x68 }, { CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc }, { CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3721), 0xc9 }, { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x481b), 0x35 }, { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x3400), 0x00 }, { CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc }, { CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 }, { CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 }, { CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 }, { CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 }, { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 } }; static const struct cci_reg_sequence ov64a40_3840x2160[] = { { CCI_REG8(0x034a), 0x05 }, { CCI_REG8(0x034b), 0x05 }, { CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x50 }, { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x08 }, { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0xba }, { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x08 }, { CCI_REG8(0x3857), 0x08 }, { CCI_REG8(0x3858), 0x10 }, { CCI_REG8(0x3859), 0x10 }, { CCI_REG8(0x4016), 0x0f }, { CCI_REG8(0x4018), 0x03 }, { CCI_REG8(0x4504), 0x1e }, { CCI_REG8(0x4523), 0x41 }, { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x12 }, { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a60), 0x68 }, { CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc }, { CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3721), 0xc9 }, { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x481b), 0x35 }, { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x3400), 0x00 }, { CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc }, { CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 }, { CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 }, { CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 }, { CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 }, { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0345), 0x90 }, { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 }, { CCI_REG8(0x5000), 0x01 } }; static const struct cci_reg_sequence ov64a40_2312_1736[] = { { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 }, { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 }, { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 }, { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 }, { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 }, { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 }, { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 }, { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 }, { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b }, { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 }, { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 }, { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a }, { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 }, { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 }, { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 }, { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 }, { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 }, { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 }, { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 }, { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 }, { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 }, { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 }, { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 }, { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 }, { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 }, { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e }, { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 }, { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 }, { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 }, { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 } }; static const struct cci_reg_sequence ov64a40_1920x1080[] = { { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 }, { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 }, { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 }, { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 }, { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 }, { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 }, { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 }, { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 }, { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b }, { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 }, { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 }, { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a }, { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 }, { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 }, { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 }, { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 }, { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 }, { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 }, { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 }, { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 }, { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 }, { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 }, { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 }, { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 }, { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 }, { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e }, { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 }, { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 }, { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 }, { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 } }; /* 456MHz MIPI link frequency with 24MHz input clock. */ static const struct cci_reg_sequence ov64a40_pll_config[] = { { OV64A40_PLL1_PRE_DIV0, 0x88 }, { OV64A40_PLL1_PRE_DIV, 0x02 }, { OV64A40_PLL1_MULTIPLIER, 0x0098 }, { OV64A40_PLL1_M_DIV, 0x01 }, { OV64A40_PLL2_SEL_BAK_SA1, 0x00 }, { OV64A40_PLL2_PRE_DIV, 0x12 }, { OV64A40_PLL2_MULTIPLIER, 0x0190 }, { OV64A40_PLL2_PRE_DIV0, 0xd7 }, { OV64A40_PLL2_DIVSP, 0x00 }, { OV64A40_PLL2_DIVDAC, 0x00 }, { OV64A40_PLL2_DACPREDIV, 0x00 } }; struct ov64a40_reglist { unsigned int num_regs; const struct cci_reg_sequence *regvals; }; struct ov64a40_subsampling { unsigned int x_odd_inc; unsigned int x_even_inc; unsigned int y_odd_inc; unsigned int y_even_inc; bool vbin; bool hbin; }; static struct ov64a40_mode { unsigned int width; unsigned int height; struct ov64a40_timings { unsigned int vts; unsigned int ppl; } timings_default[OV64A40_NUM_LINK_FREQ]; const struct ov64a40_reglist reglist; struct v4l2_rect analogue_crop; struct v4l2_rect digital_crop; struct ov64a40_subsampling subsampling; } ov64a40_modes[] = { /* Full resolution */ { .width = 9248, .height = 6944, .timings_default = { /* 2.6 FPS */ [OV64A40_LINK_FREQ_456M_ID] = { .vts = 7072, .ppl = 4072, }, /* 2 FPS */ [OV64A40_LINK_FREQ_360M_ID] = { .vts = 7072, .ppl = 5248, }, }, .reglist = { .num_regs = ARRAY_SIZE(ov64a40_9248x6944), .regvals = ov64a40_9248x6944, }, .analogue_crop = { .left = 0, .top = 0, .width = 9280, .height = 6976, }, .digital_crop = { .left = 17, .top = 16, .width = 9248, .height = 6944, }, .subsampling = { .x_odd_inc = 1, .x_even_inc = 1, .y_odd_inc = 1, .y_even_inc = 1, .vbin = false, .hbin = false, }, }, /* Analogue crop + digital crop */ { .width = 8000, .height = 6000, .timings_default = { /* 3.0 FPS */ [OV64A40_LINK_FREQ_456M_ID] = { .vts = 6400, .ppl = 3848, }, /* 2.5 FPS */ [OV64A40_LINK_FREQ_360M_ID] = { .vts = 6304, .ppl = 4736, }, }, .reglist = { .num_regs = ARRAY_SIZE(ov64a40_8000x6000), .regvals = ov64a40_8000x6000, }, .analogue_crop = { .left = 624, .top = 472, .width = 8048, .height = 6032, }, .digital_crop = { .left = 17, .top = 16, .width = 8000, .height = 6000, }, .subsampling = { .x_odd_inc = 1, .x_even_inc = 1, .y_odd_inc = 1, .y_even_inc = 1, .vbin = false, .hbin = false, }, }, /* 2x2 downscaled */ { .width = 4624, .height = 3472, .timings_default = { /* 10 FPS */ [OV64A40_LINK_FREQ_456M_ID] = { .vts = 3533, .ppl = 2112, }, /* 7 FPS */ [OV64A40_LINK_FREQ_360M_ID] = { .vts = 3939, .ppl = 2720, }, }, .reglist = { .num_regs = ARRAY_SIZE(ov64a40_4624_3472), .regvals = ov64a40_4624_3472, }, .analogue_crop = { .left = 0, .top = 0, .width = 9280, .height = 6976, }, .digital_crop = { .left = 9, .top = 8, .width = 4624, .height = 3472, }, .subsampling = { .x_odd_inc = 3, .x_even_inc = 1, .y_odd_inc = 1, .y_even_inc = 1, .vbin = true, .hbin = false, }, }, /* Analogue crop + 2x2 downscale + digital crop */ { .width = 3840, .height = 2160, .timings_default = { /* 20 FPS */ [OV64A40_LINK_FREQ_456M_ID] = { .vts = 2218, .ppl = 1690, }, /* 15 FPS */ [OV64A40_LINK_FREQ_360M_ID] = { .vts = 2270, .ppl = 2202, }, }, .reglist = { .num_regs = ARRAY_SIZE(ov64a40_3840x2160), .regvals = ov64a40_3840x2160, }, .analogue_crop = { .left = 784, .top = 1312, .width = 7712, .height = 4352, }, .digital_crop = { .left = 9, .top = 8, .width = 3840, .height = 2160, }, .subsampling = { .x_odd_inc = 3, .x_even_inc = 1, .y_odd_inc = 1, .y_even_inc = 1, .vbin = true, .hbin = false, }, }, /* 4x4 downscaled */ { .width = 2312, .height = 1736, .timings_default = { /* 30 FPS */ [OV64A40_LINK_FREQ_456M_ID] = { .vts = 1998, .ppl = 1248, }, /* 25 FPS */ [OV64A40_LINK_FREQ_360M_ID] = { .vts = 1994, .ppl = 1504, }, }, .reglist = { .num_regs = ARRAY_SIZE(ov64a40_2312_1736), .regvals = ov64a40_2312_1736, }, .analogue_crop = { .left = 0, .top = 0, .width = 9280, .height = 6976, }, .digital_crop = { .left = 5, .top = 4, .width = 2312, .height = 1736, }, .subsampling = { .x_odd_inc = 3, .x_even_inc = 1, .y_odd_inc = 3, .y_even_inc = 1, .vbin = true, .hbin = true, }, }, /* Analogue crop + 4x4 downscale + digital crop */ { .width = 1920, .height = 1080, .timings_default = { /* 60 FPS */ [OV64A40_LINK_FREQ_456M_ID] = { .vts = 1397, .ppl = 880, }, /* 45 FPS */ [OV64A40_LINK_FREQ_360M_ID] = { .vts = 1216, .ppl = 1360, }, }, .reglist = { .num_regs = ARRAY_SIZE(ov64a40_1920x1080), .regvals = ov64a40_1920x1080, }, .analogue_crop = { .left = 784, .top = 1312, .width = 7712, .height = 4352, }, .digital_crop = { .left = 7, .top = 6, .width = 1920, .height = 1080, }, .subsampling = { .x_odd_inc = 3, .x_even_inc = 1, .y_odd_inc = 3, .y_even_inc = 1, .vbin = true, .hbin = true, }, }, }; struct ov64a40 { struct device *dev; struct v4l2_subdev sd; struct media_pad pad; struct regmap *cci; struct ov64a40_mode *mode; struct clk *xclk; struct gpio_desc *reset_gpio; struct regulator_bulk_data supplies[ARRAY_SIZE(ov64a40_supply_names)]; s64 *link_frequencies; unsigned int num_link_frequencies; struct v4l2_ctrl_handler ctrl_handler; struct v4l2_ctrl *exposure; struct v4l2_ctrl *link_freq; struct v4l2_ctrl *vblank; struct v4l2_ctrl *hblank; struct v4l2_ctrl *vflip; struct v4l2_ctrl *hflip; }; static inline struct ov64a40 *sd_to_ov64a40(struct v4l2_subdev *sd) { return container_of_const(sd, struct ov64a40, sd); } static const struct ov64a40_timings * ov64a40_get_timings(struct ov64a40 *ov64a40, unsigned int link_freq_index) { s64 link_freq = ov64a40->link_frequencies[link_freq_index]; unsigned int timings_index = link_freq == OV64A40_LINK_FREQ_360M ? OV64A40_LINK_FREQ_360M_ID : OV64A40_LINK_FREQ_456M_ID; return &ov64a40->mode->timings_default[timings_index]; } static int ov64a40_program_geometry(struct ov64a40 *ov64a40) { struct ov64a40_mode *mode = ov64a40->mode; struct v4l2_rect *anacrop = &mode->analogue_crop; struct v4l2_rect *digicrop = &mode->digital_crop; const struct ov64a40_timings *timings; int ret = 0; /* Analogue crop. */ cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL0, anacrop->left, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL2, anacrop->top, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL4, anacrop->width + anacrop->left - 1, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL6, anacrop->height + anacrop->top - 1, &ret); /* ISP windowing. */ cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL10, digicrop->left, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL12, digicrop->top, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL8, digicrop->width, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLA, digicrop->height, &ret); /* Total timings. */ timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLC, timings->ppl, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLE, timings->vts, &ret); return ret; } static int ov64a40_program_subsampling(struct ov64a40 *ov64a40) { struct ov64a40_subsampling *subsampling = &ov64a40->mode->subsampling; int ret = 0; /* Skipping configuration */ cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL14, OV64A40_SKIPPING_CONFIG(subsampling->x_odd_inc, subsampling->x_even_inc), &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL15, OV64A40_SKIPPING_CONFIG(subsampling->y_odd_inc, subsampling->y_even_inc), &ret); /* Binning configuration */ cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20, OV64A40_TIMING_CTRL_20_VBIN, subsampling->vbin ? OV64A40_TIMING_CTRL_20_VBIN : 0, &ret); cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21, OV64A40_TIMING_CTRL_21_HBIN_CONF, subsampling->hbin ? OV64A40_TIMING_CTRL_21_HBIN_CONF : 0, &ret); return ret; } static int ov64a40_start_streaming(struct ov64a40 *ov64a40, struct v4l2_subdev_state *state) { const struct ov64a40_reglist *reglist = &ov64a40->mode->reglist; const struct ov64a40_timings *timings; unsigned long delay; int ret; ret = pm_runtime_resume_and_get(ov64a40->dev); if (ret < 0) return ret; ret = cci_multi_reg_write(ov64a40->cci, ov64a40_init, ARRAY_SIZE(ov64a40_init), NULL); if (ret) goto error_power_off; ret = cci_multi_reg_write(ov64a40->cci, reglist->regvals, reglist->num_regs, NULL); if (ret) goto error_power_off; ret = ov64a40_program_geometry(ov64a40); if (ret) goto error_power_off; ret = ov64a40_program_subsampling(ov64a40); if (ret) goto error_power_off; ret = __v4l2_ctrl_handler_setup(&ov64a40->ctrl_handler); if (ret) goto error_power_off; ret = cci_write(ov64a40->cci, OV64A40_REG_SMIA, OV64A40_REG_SMIA_STREAMING, NULL); if (ret) goto error_power_off; /* Link frequency and flips cannot change while streaming. */ __v4l2_ctrl_grab(ov64a40->link_freq, true); __v4l2_ctrl_grab(ov64a40->vflip, true); __v4l2_ctrl_grab(ov64a40->hflip, true); /* delay: max(4096 xclk pulses, 150usec) + exposure time */ timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val); delay = DIV_ROUND_UP(4096, OV64A40_XCLK_FREQ / 1000 / 1000); delay = max(delay, 150ul); /* The sensor has an internal x4 multiplier on the line length. */ delay += DIV_ROUND_UP(timings->ppl * 4 * ov64a40->exposure->cur.val, OV64A40_PIXEL_RATE / 1000 / 1000); fsleep(delay); return 0; error_power_off: pm_runtime_mark_last_busy(ov64a40->dev); pm_runtime_put_autosuspend(ov64a40->dev); return ret; } static int ov64a40_stop_streaming(struct ov64a40 *ov64a40, struct v4l2_subdev_state *state) { cci_update_bits(ov64a40->cci, OV64A40_REG_SMIA, BIT(0), 0, NULL); pm_runtime_mark_last_busy(ov64a40->dev); pm_runtime_put_autosuspend(ov64a40->dev); __v4l2_ctrl_grab(ov64a40->link_freq, false); __v4l2_ctrl_grab(ov64a40->vflip, false); __v4l2_ctrl_grab(ov64a40->hflip, false); return 0; } static int ov64a40_set_stream(struct v4l2_subdev *sd, int enable) { struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); struct v4l2_subdev_state *state; int ret; state = v4l2_subdev_lock_and_get_active_state(sd); if (enable) ret = ov64a40_start_streaming(ov64a40, state); else ret = ov64a40_stop_streaming(ov64a40, state); v4l2_subdev_unlock_state(state); return ret; } static const struct v4l2_subdev_video_ops ov64a40_video_ops = { .s_stream = ov64a40_set_stream, }; static u32 ov64a40_mbus_code(struct ov64a40 *ov64a40) { unsigned int index = ov64a40->hflip->val << 1 | ov64a40->vflip->val; return ov64a40_mbus_codes[index]; } static void ov64a40_update_pad_fmt(struct ov64a40 *ov64a40, struct ov64a40_mode *mode, struct v4l2_mbus_framefmt *fmt) { fmt->code = ov64a40_mbus_code(ov64a40); fmt->width = mode->width; fmt->height = mode->height; fmt->field = V4L2_FIELD_NONE; fmt->colorspace = V4L2_COLORSPACE_RAW; fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; fmt->xfer_func = V4L2_XFER_FUNC_NONE; fmt->ycbcr_enc = V4L2_YCBCR_ENC_601; } static int ov64a40_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *state) { struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); struct v4l2_mbus_framefmt *format; struct v4l2_rect *crop; format = v4l2_subdev_state_get_format(state, 0); ov64a40_update_pad_fmt(ov64a40, &ov64a40_modes[0], format); crop = v4l2_subdev_state_get_crop(state, 0); crop->top = OV64A40_PIXEL_ARRAY_TOP; crop->left = OV64A40_PIXEL_ARRAY_LEFT; crop->width = OV64A40_PIXEL_ARRAY_WIDTH; crop->height = OV64A40_PIXEL_ARRAY_HEIGHT; return 0; } static int ov64a40_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_mbus_code_enum *code) { struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); if (code->index) return -EINVAL; code->code = ov64a40_mbus_code(ov64a40); return 0; } static int ov64a40_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_frame_size_enum *fse) { struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); struct ov64a40_mode *mode; u32 code; if (fse->index >= ARRAY_SIZE(ov64a40_modes)) return -EINVAL; code = ov64a40_mbus_code(ov64a40); if (fse->code != code) return -EINVAL; mode = &ov64a40_modes[fse->index]; fse->min_width = mode->width; fse->max_width = mode->width; fse->min_height = mode->height; fse->max_height = mode->height; return 0; } static int ov64a40_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_selection *sel) { switch (sel->target) { case V4L2_SEL_TGT_CROP: sel->r = *v4l2_subdev_state_get_crop(state, 0); return 0; case V4L2_SEL_TGT_NATIVE_SIZE: sel->r.top = 0; sel->r.left = 0; sel->r.width = OV64A40_NATIVE_WIDTH; sel->r.height = OV64A40_NATIVE_HEIGHT; return 0; case V4L2_SEL_TGT_CROP_DEFAULT: case V4L2_SEL_TGT_CROP_BOUNDS: sel->r.top = OV64A40_PIXEL_ARRAY_TOP; sel->r.left = OV64A40_PIXEL_ARRAY_LEFT; sel->r.width = OV64A40_PIXEL_ARRAY_WIDTH; sel->r.height = OV64A40_PIXEL_ARRAY_HEIGHT; return 0; } return -EINVAL; } static int ov64a40_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_format *fmt) { struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); struct v4l2_mbus_framefmt *format; struct ov64a40_mode *mode; mode = v4l2_find_nearest_size(ov64a40_modes, ARRAY_SIZE(ov64a40_modes), width, height, fmt->format.width, fmt->format.height); ov64a40_update_pad_fmt(ov64a40, mode, &fmt->format); format = v4l2_subdev_state_get_format(state, 0); if (ov64a40->mode == mode && format->code == fmt->format.code) return 0; if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { const struct ov64a40_timings *timings; int vblank_max, vblank_def; int hblank_val; int exp_max; ov64a40->mode = mode; *v4l2_subdev_state_get_crop(state, 0) = mode->analogue_crop; /* Update control limits according to the new mode. */ timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val); vblank_max = OV64A40_VTS_MAX - mode->height; vblank_def = timings->vts - mode->height; __v4l2_ctrl_modify_range(ov64a40->vblank, OV64A40_VBLANK_MIN, vblank_max, 1, vblank_def); __v4l2_ctrl_s_ctrl(ov64a40->vblank, vblank_def); exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN; __v4l2_ctrl_modify_range(ov64a40->exposure, OV64A40_EXPOSURE_MIN, exp_max, 1, OV64A40_EXPOSURE_MIN); hblank_val = timings->ppl * 4 - mode->width; __v4l2_ctrl_modify_range(ov64a40->hblank, hblank_val, hblank_val, 1, hblank_val); } *format = fmt->format; return 0; } static const struct v4l2_subdev_pad_ops ov64a40_pad_ops = { .enum_mbus_code = ov64a40_enum_mbus_code, .enum_frame_size = ov64a40_enum_frame_size, .get_fmt = v4l2_subdev_get_fmt, .set_fmt = ov64a40_set_format, .get_selection = ov64a40_get_selection, }; static const struct v4l2_subdev_core_ops ov64a40_core_ops = { .subscribe_event = v4l2_ctrl_subdev_subscribe_event, .unsubscribe_event = v4l2_event_subdev_unsubscribe, }; static const struct v4l2_subdev_ops ov64a40_subdev_ops = { .core = &ov64a40_core_ops, .video = &ov64a40_video_ops, .pad = &ov64a40_pad_ops, }; static const struct v4l2_subdev_internal_ops ov64a40_internal_ops = { .init_state = ov64a40_init_state, }; static int ov64a40_power_on(struct device *dev) { struct v4l2_subdev *sd = dev_get_drvdata(dev); struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); int ret; ret = clk_prepare_enable(ov64a40->xclk); if (ret) return ret; ret = regulator_bulk_enable(ARRAY_SIZE(ov64a40_supply_names), ov64a40->supplies); if (ret) { clk_disable_unprepare(ov64a40->xclk); dev_err(dev, "Failed to enable regulators: %d\n", ret); return ret; } gpiod_set_value_cansleep(ov64a40->reset_gpio, 0); fsleep(5000); return 0; } static int ov64a40_power_off(struct device *dev) { struct v4l2_subdev *sd = dev_get_drvdata(dev); struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); gpiod_set_value_cansleep(ov64a40->reset_gpio, 1); regulator_bulk_disable(ARRAY_SIZE(ov64a40_supply_names), ov64a40->supplies); clk_disable_unprepare(ov64a40->xclk); return 0; } static int ov64a40_link_freq_config(struct ov64a40 *ov64a40, int link_freq_id) { s64 link_frequency; int ret = 0; /* Default 456MHz with 24MHz input clock. */ cci_multi_reg_write(ov64a40->cci, ov64a40_pll_config, ARRAY_SIZE(ov64a40_pll_config), &ret); /* Decrease the PLL1 multiplier to obtain 360MHz mipi link frequency. */ link_frequency = ov64a40->link_frequencies[link_freq_id]; if (link_frequency == OV64A40_LINK_FREQ_360M) cci_write(ov64a40->cci, OV64A40_PLL1_MULTIPLIER, 0x0078, &ret); return ret; } static int ov64a40_set_ctrl(struct v4l2_ctrl *ctrl) { struct ov64a40 *ov64a40 = container_of(ctrl->handler, struct ov64a40, ctrl_handler); int pm_status; int ret = 0; if (ctrl->id == V4L2_CID_VBLANK) { int exp_max = ov64a40->mode->height + ctrl->val - OV64A40_EXPOSURE_MARGIN; int exp_val = min(ov64a40->exposure->cur.val, exp_max); __v4l2_ctrl_modify_range(ov64a40->exposure, ov64a40->exposure->minimum, exp_max, 1, exp_val); } pm_status = pm_runtime_get_if_active(ov64a40->dev); if (!pm_status) return 0; switch (ctrl->id) { case V4L2_CID_EXPOSURE: ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_EXPO, ctrl->val, NULL); break; case V4L2_CID_ANALOGUE_GAIN: ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_GAIN, ctrl->val << 1, NULL); break; case V4L2_CID_VBLANK: { int vts = ctrl->val + ov64a40->mode->height; cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_LOW, vts, &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_MID, (vts >> 8), &ret); cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_HIGH, (vts >> 16), &ret); break; } case V4L2_CID_VFLIP: ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20, OV64A40_TIMING_CTRL_20_VFLIP, ctrl->val << 2, NULL); break; case V4L2_CID_HFLIP: ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21, OV64A40_TIMING_CTRL_21_HFLIP, ctrl->val ? 0 : OV64A40_TIMING_CTRL_21_HFLIP, NULL); break; case V4L2_CID_TEST_PATTERN: ret = cci_write(ov64a40->cci, OV64A40_REG_TEST_PATTERN, ov64a40_test_pattern_val[ctrl->val], NULL); break; case V4L2_CID_LINK_FREQ: ret = ov64a40_link_freq_config(ov64a40, ctrl->val); break; default: dev_err(ov64a40->dev, "Unhandled control: %#x\n", ctrl->id); ret = -EINVAL; break; } if (pm_status > 0) { pm_runtime_mark_last_busy(ov64a40->dev); pm_runtime_put_autosuspend(ov64a40->dev); } return ret; } static const struct v4l2_ctrl_ops ov64a40_ctrl_ops = { .s_ctrl = ov64a40_set_ctrl, }; static int ov64a40_init_controls(struct ov64a40 *ov64a40) { int exp_max, hblank_val, vblank_max, vblank_def; struct v4l2_ctrl_handler *hdlr = &ov64a40->ctrl_handler; struct v4l2_fwnode_device_properties props; const struct ov64a40_timings *timings; int ret; ret = v4l2_ctrl_handler_init(hdlr, 11); if (ret) return ret; v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_PIXEL_RATE, OV64A40_PIXEL_RATE, OV64A40_PIXEL_RATE, 1, OV64A40_PIXEL_RATE); ov64a40->link_freq = v4l2_ctrl_new_int_menu(hdlr, &ov64a40_ctrl_ops, V4L2_CID_LINK_FREQ, ov64a40->num_link_frequencies - 1, 0, ov64a40->link_frequencies); v4l2_ctrl_new_std_menu_items(hdlr, &ov64a40_ctrl_ops, V4L2_CID_TEST_PATTERN, ARRAY_SIZE(ov64a40_test_pattern_menu) - 1, 0, 0, ov64a40_test_pattern_menu); timings = ov64a40_get_timings(ov64a40, 0); exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN; ov64a40->exposure = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_EXPOSURE, OV64A40_EXPOSURE_MIN, exp_max, 1, OV64A40_EXPOSURE_MIN); hblank_val = timings->ppl * 4 - ov64a40->mode->width; ov64a40->hblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_HBLANK, hblank_val, hblank_val, 1, hblank_val); if (ov64a40->hblank) ov64a40->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; vblank_def = timings->vts - ov64a40->mode->height; vblank_max = OV64A40_VTS_MAX - ov64a40->mode->height; ov64a40->vblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_VBLANK, OV64A40_VBLANK_MIN, vblank_max, 1, vblank_def); v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, OV64A40_ANA_GAIN_MIN, OV64A40_ANA_GAIN_MAX, 1, OV64A40_ANA_GAIN_DEFAULT); ov64a40->hflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); if (ov64a40->hflip) ov64a40->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; ov64a40->vflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); if (ov64a40->vflip) ov64a40->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; if (hdlr->error) { ret = hdlr->error; dev_err(ov64a40->dev, "control init failed: %d\n", ret); goto error_free_hdlr; } ret = v4l2_fwnode_device_parse(ov64a40->dev, &props); if (ret) goto error_free_hdlr; ret = v4l2_ctrl_new_fwnode_properties(hdlr, &ov64a40_ctrl_ops, &props); if (ret) goto error_free_hdlr; ov64a40->sd.ctrl_handler = hdlr; return 0; error_free_hdlr: v4l2_ctrl_handler_free(hdlr); return ret; } static int ov64a40_identify(struct ov64a40 *ov64a40) { int ret; u64 id; ret = cci_read(ov64a40->cci, OV64A40_REG_CHIP_ID, &id, NULL); if (ret) { dev_err(ov64a40->dev, "Failed to read chip id: %d\n", ret); return ret; } if (id != OV64A40_CHIP_ID) { dev_err(ov64a40->dev, "chip id mismatch: %#llx\n", id); return -ENODEV; } dev_dbg(ov64a40->dev, "OV64A40 chip identified: %#llx\n", id); return 0; } static int ov64a40_parse_dt(struct ov64a40 *ov64a40) { struct v4l2_fwnode_endpoint v4l2_fwnode = { .bus_type = V4L2_MBUS_CSI2_DPHY }; struct fwnode_handle *endpoint; unsigned int i; int ret; endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(ov64a40->dev), NULL); if (!endpoint) { dev_err(ov64a40->dev, "Failed to find endpoint\n"); return -EINVAL; } ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &v4l2_fwnode); fwnode_handle_put(endpoint); if (ret) { dev_err(ov64a40->dev, "Failed to parse endpoint\n"); return ret; } if (v4l2_fwnode.bus.mipi_csi2.num_data_lanes != 2) { dev_err(ov64a40->dev, "Unsupported number of data lanes: %u\n", v4l2_fwnode.bus.mipi_csi2.num_data_lanes); v4l2_fwnode_endpoint_free(&v4l2_fwnode); return -EINVAL; } if (!v4l2_fwnode.nr_of_link_frequencies) { dev_warn(ov64a40->dev, "no link frequencies defined\n"); v4l2_fwnode_endpoint_free(&v4l2_fwnode); return -EINVAL; } if (v4l2_fwnode.nr_of_link_frequencies > 2) { dev_warn(ov64a40->dev, "Unsupported number of link frequencies\n"); v4l2_fwnode_endpoint_free(&v4l2_fwnode); return -EINVAL; } ov64a40->link_frequencies = devm_kcalloc(ov64a40->dev, v4l2_fwnode.nr_of_link_frequencies, sizeof(v4l2_fwnode.link_frequencies[0]), GFP_KERNEL); if (!ov64a40->link_frequencies) { v4l2_fwnode_endpoint_free(&v4l2_fwnode); return -ENOMEM; } ov64a40->num_link_frequencies = v4l2_fwnode.nr_of_link_frequencies; for (i = 0; i < v4l2_fwnode.nr_of_link_frequencies; ++i) { if (v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_360M && v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_456M) { dev_err(ov64a40->dev, "Unsupported link frequency %lld\n", v4l2_fwnode.link_frequencies[i]); v4l2_fwnode_endpoint_free(&v4l2_fwnode); return -EINVAL; } ov64a40->link_frequencies[i] = v4l2_fwnode.link_frequencies[i]; } v4l2_fwnode_endpoint_free(&v4l2_fwnode); return 0; } static int ov64a40_get_regulators(struct ov64a40 *ov64a40) { struct i2c_client *client = v4l2_get_subdevdata(&ov64a40->sd); unsigned int i; for (i = 0; i < ARRAY_SIZE(ov64a40_supply_names); i++) ov64a40->supplies[i].supply = ov64a40_supply_names[i]; return devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(ov64a40_supply_names), ov64a40->supplies); } static int ov64a40_probe(struct i2c_client *client) { struct ov64a40 *ov64a40; u32 xclk_freq; int ret; ov64a40 = devm_kzalloc(&client->dev, sizeof(*ov64a40), GFP_KERNEL); if (!ov64a40) return -ENOMEM; ov64a40->dev = &client->dev; v4l2_i2c_subdev_init(&ov64a40->sd, client, &ov64a40_subdev_ops); ov64a40->cci = devm_cci_regmap_init_i2c(client, 16); if (IS_ERR(ov64a40->cci)) { dev_err(&client->dev, "Failed to initialize CCI\n"); return PTR_ERR(ov64a40->cci); } ov64a40->xclk = devm_clk_get(&client->dev, NULL); if (IS_ERR(ov64a40->xclk)) return dev_err_probe(&client->dev, PTR_ERR(ov64a40->xclk), "Failed to get clock\n"); xclk_freq = clk_get_rate(ov64a40->xclk); if (xclk_freq != OV64A40_XCLK_FREQ) { dev_err(&client->dev, "Unsupported xclk frequency %u\n", xclk_freq); return -EINVAL; } ret = ov64a40_get_regulators(ov64a40); if (ret) return ret; ov64a40->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(ov64a40->reset_gpio)) return dev_err_probe(&client->dev, PTR_ERR(ov64a40->reset_gpio), "Failed to get reset gpio\n"); ret = ov64a40_parse_dt(ov64a40); if (ret) return ret; ret = ov64a40_power_on(&client->dev); if (ret) return ret; ret = ov64a40_identify(ov64a40); if (ret) goto error_poweroff; ov64a40->mode = &ov64a40_modes[0]; pm_runtime_set_active(&client->dev); pm_runtime_get_noresume(&client->dev); pm_runtime_enable(&client->dev); pm_runtime_set_autosuspend_delay(&client->dev, 1000); pm_runtime_use_autosuspend(&client->dev); ret = ov64a40_init_controls(ov64a40); if (ret) goto error_poweroff; /* Initialize subdev */ ov64a40->sd.internal_ops = &ov64a40_internal_ops; ov64a40->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; ov64a40->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; ov64a40->pad.flags = MEDIA_PAD_FL_SOURCE; ret = media_entity_pads_init(&ov64a40->sd.entity, 1, &ov64a40->pad); if (ret) { dev_err(&client->dev, "failed to init entity pads: %d\n", ret); goto error_handler_free; } ov64a40->sd.state_lock = ov64a40->ctrl_handler.lock; ret = v4l2_subdev_init_finalize(&ov64a40->sd); if (ret < 0) { dev_err(&client->dev, "subdev init error: %d\n", ret); goto error_media_entity; } ret = v4l2_async_register_subdev_sensor(&ov64a40->sd); if (ret < 0) { dev_err(&client->dev, "failed to register sensor sub-device: %d\n", ret); goto error_subdev_cleanup; } pm_runtime_mark_last_busy(&client->dev); pm_runtime_put_autosuspend(&client->dev); return 0; error_subdev_cleanup: v4l2_subdev_cleanup(&ov64a40->sd); error_media_entity: media_entity_cleanup(&ov64a40->sd.entity); error_handler_free: v4l2_ctrl_handler_free(ov64a40->sd.ctrl_handler); error_poweroff: ov64a40_power_off(&client->dev); pm_runtime_set_suspended(&client->dev); return ret; } static void ov64a40_remove(struct i2c_client *client) { struct v4l2_subdev *sd = i2c_get_clientdata(client); v4l2_async_unregister_subdev(sd); v4l2_subdev_cleanup(sd); media_entity_cleanup(&sd->entity); v4l2_ctrl_handler_free(sd->ctrl_handler); pm_runtime_disable(&client->dev); if (!pm_runtime_status_suspended(&client->dev)) ov64a40_power_off(&client->dev); pm_runtime_set_suspended(&client->dev); } static const struct of_device_id ov64a40_of_ids[] = { { .compatible = "ovti,ov64a40" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, ov64a40_of_ids); static const struct dev_pm_ops ov64a40_pm_ops = { SET_RUNTIME_PM_OPS(ov64a40_power_off, ov64a40_power_on, NULL) }; static struct i2c_driver ov64a40_i2c_driver = { .driver = { .name = "ov64a40", .of_match_table = ov64a40_of_ids, .pm = &ov64a40_pm_ops, }, .probe = ov64a40_probe, .remove = ov64a40_remove, }; module_i2c_driver(ov64a40_i2c_driver); MODULE_AUTHOR("Jacopo Mondi <jacopo.mondi@ideasonboard.com>"); MODULE_DESCRIPTION("OmniVision OV64A40 sensor driver"); MODULE_LICENSE("GPL");
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