Contributors: 14
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Radhakrishna Sripada |
74 |
34.10% |
2 |
5.41% |
| Mika Kahola |
36 |
16.59% |
8 |
21.62% |
| Lucas De Marchi |
24 |
11.06% |
2 |
5.41% |
| Jani Nikula |
22 |
10.14% |
5 |
13.51% |
| Paulo Zanoni |
17 |
7.83% |
3 |
8.11% |
| Ville Syrjälä |
14 |
6.45% |
6 |
16.22% |
| Maarten Lankhorst |
10 |
4.61% |
2 |
5.41% |
| Ander Conselvan de Oliveira |
7 |
3.23% |
2 |
5.41% |
| Shashank Sharma |
4 |
1.84% |
1 |
2.70% |
| Daniel Vetter |
3 |
1.38% |
2 |
5.41% |
| Chris Wilson |
2 |
0.92% |
1 |
2.70% |
| Imre Deak |
2 |
0.92% |
1 |
2.70% |
| José Roberto de Souza |
1 |
0.46% |
1 |
2.70% |
| Dave Airlie |
1 |
0.46% |
1 |
2.70% |
| Total |
217 |
|
37 |
|
// SPDX-License-Identifier: MIT
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __INTEL_CX0_PHY_H__
#define __INTEL_CX0_PHY_H__
#include <linux/types.h>
enum icl_port_dpll_id;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_cx0pll_state;
struct intel_display;
struct intel_encoder;
struct intel_hdmi;
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_cx0pll_state *pll_state);
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_cx0pll_state *pll_state);
void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state);
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
const struct intel_cx0pll_state *b);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */