Contributors: 6
Author Tokens Token Proportion Commits Commit Proportion
Thierry Reding 156 49.21% 11 64.71%
Arto Merilainen 139 43.85% 1 5.88%
Mikko Perttunen 11 3.47% 2 11.76%
Dmitry Osipenko 6 1.89% 1 5.88%
Daniel Vetter 3 0.95% 1 5.88%
Thomas Gleixner 2 0.63% 1 5.88%
Total 317 17 


/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Tegra host1x GEM implementation
 *
 * Copyright (c) 2012-2013, NVIDIA Corporation.
 */

#ifndef __HOST1X_GEM_H
#define __HOST1X_GEM_H

#include <linux/host1x.h>

#include <drm/drm.h>
#include <drm/drm_gem.h>

#define TEGRA_BO_BOTTOM_UP (1 << 0)

enum tegra_bo_tiling_mode {
	TEGRA_BO_TILING_MODE_PITCH,
	TEGRA_BO_TILING_MODE_TILED,
	TEGRA_BO_TILING_MODE_BLOCK,
};

enum tegra_bo_sector_layout {
	TEGRA_BO_SECTOR_LAYOUT_TEGRA,
	TEGRA_BO_SECTOR_LAYOUT_GPU,
};

struct tegra_bo_tiling {
	enum tegra_bo_tiling_mode mode;
	unsigned long value;
	enum tegra_bo_sector_layout sector_layout;
};

/*
 * How memory is referenced within a tegra_bo:
 *
 * Buffer source  | Mapping API(*)  | Fields
 * ---------------+-----------------+---------------
 * Allocated here | DMA API         | iova (IOVA mapped to drm->dev), vaddr (CPU VA)
 *
 * Allocated here | IOMMU API       | pages/num_pages (Phys. memory), sgt (Mapped to drm->dev),
 *                                  | iova/size (Mapped to domain)
 *
 * Imported       | DMA API         | dma_buf (Imported dma_buf)
 *
 * Imported       | IOMMU API       | dma_buf (Imported dma_buf),
 *                                  | gem->import_attach (Attachment on drm->dev),
 *                                  | sgt (Mapped to drm->dev)
 *                                  | iova/size (Mapped to domain)
 *
 * (*) If tegra->domain is set, i.e. TegraDRM IOMMU domain is directly managed through IOMMU API,
 *     this is IOMMU API. Otherwise DMA API.
 */
struct tegra_bo {
	struct drm_gem_object gem;
	struct host1x_bo base;
	unsigned long flags;
	struct sg_table *sgt;
	dma_addr_t iova;
	void *vaddr;
	struct dma_buf *dma_buf;

	struct drm_mm_node *mm;
	unsigned long num_pages;
	struct page **pages;
	/* size of IOMMU mapping */
	size_t size;

	struct tegra_bo_tiling tiling;
};

static inline struct tegra_bo *to_tegra_bo(struct drm_gem_object *gem)
{
	return container_of(gem, struct tegra_bo, gem);
}

static inline struct tegra_bo *host1x_to_tegra_bo(struct host1x_bo *bo)
{
	return container_of(bo, struct tegra_bo, base);
}

struct tegra_bo *tegra_bo_create(struct drm_device *drm, size_t size,
				 unsigned long flags);
struct tegra_bo *tegra_bo_create_with_handle(struct drm_file *file,
					     struct drm_device *drm,
					     size_t size,
					     unsigned long flags,
					     u32 *handle);
void tegra_bo_free_object(struct drm_gem_object *gem);
int tegra_bo_dumb_create(struct drm_file *file, struct drm_device *drm,
			 struct drm_mode_create_dumb *args);

extern const struct vm_operations_struct tegra_bo_vm_ops;

int __tegra_gem_mmap(struct drm_gem_object *gem, struct vm_area_struct *vma);
int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma);

struct dma_buf *tegra_gem_prime_export(struct drm_gem_object *gem,
				       int flags);
struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm,
					      struct dma_buf *buf);

struct host1x_bo *tegra_gem_lookup(struct drm_file *file, u32 handle);

#endif