Cregit: Linux 6.13: qcom,ipq5424-gcc.h

Contributors: 1
Author	Tokens	Token Proportion	Commits	Commit Proportion
Sricharan Ramabadhran	1206	100.00%	1	100.00%
Total	1206		1

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H
#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H

#define GCC_QUPV3_BCR				0
#define GCC_QUPV3_I2C0_BCR			1
#define GCC_QUPV3_UART0_BCR			2
#define GCC_QUPV3_I2C1_BCR			3
#define GCC_QUPV3_UART1_BCR			4
#define GCC_QUPV3_SPI0_BCR			5
#define GCC_QUPV3_SPI1_BCR			6
#define GCC_IMEM_BCR				7
#define GCC_TME_BCR				8
#define GCC_DDRSS_BCR				9
#define GCC_PRNG_BCR				10
#define GCC_BOOT_ROM_BCR			11
#define GCC_NSS_BCR				12
#define GCC_MDIO_BCR				13
#define GCC_UNIPHY0_BCR				14
#define GCC_UNIPHY1_BCR				15
#define GCC_UNIPHY2_BCR				16
#define GCC_WCSS_BCR				17
#define GCC_SEC_CTRL_BCR			19
#define GCC_TME_SEC_BUS_BCR			20
#define GCC_ADSS_BCR				21
#define GCC_LPASS_BCR				22
#define GCC_PCIE0_BCR				23
#define GCC_PCIE0_LINK_DOWN_BCR			24
#define GCC_PCIE0PHY_PHY_BCR			25
#define GCC_PCIE0_PHY_BCR			26
#define GCC_PCIE1_BCR				27
#define GCC_PCIE1_LINK_DOWN_BCR			28
#define GCC_PCIE1PHY_PHY_BCR			29
#define GCC_PCIE1_PHY_BCR			30
#define GCC_PCIE2_BCR				31
#define GCC_PCIE2_LINK_DOWN_BCR			32
#define GCC_PCIE2PHY_PHY_BCR			33
#define GCC_PCIE2_PHY_BCR			34
#define GCC_PCIE3_BCR				35
#define GCC_PCIE3_LINK_DOWN_BCR			36
#define GCC_PCIE3PHY_PHY_BCR			37
#define GCC_PCIE3_PHY_BCR			38
#define GCC_USB_BCR				39
#define GCC_QUSB2_0_PHY_BCR			40
#define GCC_USB0_PHY_BCR			41
#define GCC_USB3PHY_0_PHY_BCR			42
#define GCC_QDSS_BCR				43
#define GCC_SNOC_BCR				44
#define GCC_ANOC_BCR				45
#define GCC_PCNOC_BCR				46
#define GCC_PCNOC_BUS_TIMEOUT0_BCR		47
#define GCC_PCNOC_BUS_TIMEOUT1_BCR		48
#define GCC_PCNOC_BUS_TIMEOUT2_BCR		49
#define GCC_PCNOC_BUS_TIMEOUT3_BCR		50
#define GCC_PCNOC_BUS_TIMEOUT4_BCR		51
#define GCC_PCNOC_BUS_TIMEOUT5_BCR		52
#define GCC_PCNOC_BUS_TIMEOUT6_BCR		53
#define GCC_PCNOC_BUS_TIMEOUT7_BCR		54
#define GCC_PCNOC_BUS_TIMEOUT8_BCR		55
#define GCC_PCNOC_BUS_TIMEOUT9_BCR		56
#define GCC_QPIC_BCR				57
#define GCC_SDCC_BCR				58
#define GCC_DCC_BCR				59
#define GCC_SPDM_BCR				60
#define GCC_MPM_BCR				61
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	62
#define GCC_RBCPR_BCR				63
#define GCC_CMN_BLK_BCR				64
#define GCC_TCSR_BCR				65
#define GCC_TLMM_BCR				66
#define GCC_QUPV3_AHB_MST_ARES			67
#define GCC_QUPV3_CORE_ARES			68
#define GCC_QUPV3_2X_CORE_ARES			69
#define GCC_QUPV3_SLEEP_ARES			70
#define GCC_QUPV3_AHB_SLV_ARES			71
#define GCC_QUPV3_I2C0_ARES			72
#define GCC_QUPV3_UART0_ARES			73
#define GCC_QUPV3_I2C1_ARES			74
#define GCC_QUPV3_UART1_ARES			75
#define GCC_QUPV3_SPI0_ARES			76
#define GCC_QUPV3_SPI1_ARES			77
#define GCC_DEBUG_ARES				78
#define GCC_GP1_ARES				79
#define GCC_GP2_ARES				80
#define GCC_GP3_ARES				81
#define GCC_IMEM_AXI_ARES			82
#define GCC_IMEM_CFG_AHB_ARES			83
#define GCC_TME_ARES				84
#define GCC_TME_TS_ARES				85
#define GCC_TME_SLOW_ARES			86
#define GCC_TME_RTC_TOGGLE_ARES			87
#define GCC_TIC_ARES				88
#define GCC_PRNG_AHB_ARES			89
#define GCC_BOOT_ROM_AHB_ARES			90
#define GCC_NSSNOC_ATB_ARES			91
#define GCC_NSS_TS_ARES				92
#define GCC_NSSNOC_QOSGEN_REF_ARES		93
#define GCC_NSSNOC_TIMEOUT_REF_ARES		94
#define GCC_NSSNOC_MEMNOC_ARES			95
#define GCC_NSSNOC_SNOC_ARES			96
#define GCC_NSSCFG_ARES				97
#define GCC_NSSNOC_NSSCC_ARES			98
#define GCC_NSSCC_ARES				99
#define GCC_MDIO_AHB_ARES			100
#define GCC_UNIPHY0_SYS_ARES			101
#define GCC_UNIPHY0_AHB_ARES			102
#define GCC_UNIPHY1_SYS_ARES			103
#define GCC_UNIPHY1_AHB_ARES			104
#define GCC_UNIPHY2_SYS_ARES			105
#define GCC_UNIPHY2_AHB_ARES			106
#define GCC_NSSNOC_XO_DCD_ARES			107
#define GCC_NSSNOC_SNOC_1_ARES			108
#define GCC_NSSNOC_PCNOC_1_ARES			109
#define GCC_NSSNOC_MEMNOC_1_ARES		110
#define GCC_DDRSS_ATB_ARES			111
#define GCC_DDRSS_AHB_ARES			112
#define GCC_GEMNOC_AHB_ARES			113
#define GCC_GEMNOC_Q6_AXI_ARES			114
#define GCC_GEMNOC_NSSNOC_ARES			115
#define GCC_GEMNOC_SNOC_ARES			116
#define GCC_GEMNOC_APSS_ARES			117
#define GCC_GEMNOC_QOSGEN_EXTREF_ARES		118
#define GCC_GEMNOC_TS_ARES			119
#define GCC_DDRSS_SMS_SLOW_ARES			120
#define GCC_GEMNOC_CNOC_ARES			121
#define GCC_GEMNOC_XO_DBG_ARES			122
#define GCC_GEMNOC_ANOC_ARES			123
#define GCC_DDRSS_LLCC_ATB_ARES			124
#define GCC_LLCC_TPDM_CFG_ARES			125
#define GCC_TME_BUS_ARES			126
#define GCC_SEC_CTRL_ACC_ARES			127
#define GCC_SEC_CTRL_ARES			128
#define GCC_SEC_CTRL_SENSE_ARES			129
#define GCC_SEC_CTRL_AHB_ARES			130
#define GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES	131
#define GCC_ADSS_PWM_ARES			132
#define GCC_TME_ATB_ARES			133
#define GCC_TME_DBGAPB_ARES			134
#define GCC_TME_DEBUG_ARES			135
#define GCC_TME_AT_ARES				136
#define GCC_TME_APB_ARES			137
#define GCC_TME_DMI_DBG_HS_ARES			138
#define GCC_APSS_AHB_ARES			139
#define GCC_APSS_AXI_ARES			140
#define GCC_CPUSS_TRIG_ARES			141
#define GCC_APSS_DBG_ARES			142
#define GCC_APSS_TS_ARES			143
#define GCC_APSS_ATB_ARES			144
#define GCC_Q6_AXIM_ARES			145
#define GCC_Q6_AXIS_ARES			146
#define GCC_Q6_AHB_ARES				147
#define GCC_Q6_AHB_S_ARES			148
#define GCC_Q6SS_ATBM_ARES			149
#define GCC_Q6_TSCTR_1TO2_ARES			150
#define GCC_Q6SS_PCLKDBG_ARES			151
#define GCC_Q6SS_TRIG_ARES			152
#define GCC_Q6SS_BOOT_CBCR_ARES			153
#define GCC_WCSS_DBG_IFC_APB_ARES		154
#define GCC_WCSS_DBG_IFC_ATB_ARES		155
#define GCC_WCSS_DBG_IFC_NTS_ARES		156
#define GCC_WCSS_DBG_IFC_DAPBUS_ARES		157
#define GCC_WCSS_DBG_IFC_APB_BDG_ARES		158
#define GCC_WCSS_DBG_IFC_NTS_BDG_ARES		159
#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES	160
#define GCC_WCSS_ECAHB_ARES			161
#define GCC_WCSS_ACMT_ARES			162
#define GCC_WCSS_AHB_S_ARES			163
#define GCC_WCSS_AXI_M_ARES			164
#define GCC_PCNOC_WAPSS_ARES			165
#define GCC_SNOC_WAPSS_ARES			166
#define GCC_LPASS_SWAY_ARES			167
#define GCC_LPASS_CORE_AXIM_ARES		168
#define GCC_PCIE0_AHB_ARES			169
#define GCC_PCIE0_AXI_M_ARES			170
#define GCC_PCIE0_AXI_S_ARES			171
#define GCC_PCIE0_AXI_S_BRIDGE_ARES		172
#define GCC_PCIE0_PIPE_ARES			173
#define GCC_PCIE0_AUX_ARES			174
#define GCC_PCIE1_AHB_ARES			175
#define GCC_PCIE1_AXI_M_ARES			176
#define GCC_PCIE1_AXI_S_ARES			177
#define GCC_PCIE1_AXI_S_BRIDGE_ARES		178
#define GCC_PCIE1_PIPE_ARES			179
#define GCC_PCIE1_AUX_ARES			180
#define GCC_PCIE2_AHB_ARES			181
#define GCC_PCIE2_AXI_M_ARES			182
#define GCC_PCIE2_AXI_S_ARES			183
#define GCC_PCIE2_AXI_S_BRIDGE_ARES		184
#define GCC_PCIE2_PIPE_ARES			185
#define GCC_PCIE2_AUX_ARES			186
#define GCC_PCIE3_AHB_ARES			187
#define GCC_PCIE3_AXI_M_ARES			188
#define GCC_PCIE3_AXI_S_ARES			189
#define GCC_PCIE3_AXI_S_BRIDGE_ARES		190
#define GCC_PCIE3_PIPE_ARES			191
#define GCC_PCIE3_AUX_ARES			192
#define GCC_USB0_MASTER_ARES			193
#define GCC_USB0_AUX_ARES			194
#define GCC_USB0_MOCK_UTMI_ARES			195
#define GCC_USB0_PIPE_ARES			196
#define GCC_USB0_SLEEP_ARES			197
#define GCC_USB0_PHY_CFG_AHB_ARES		198
#define GCC_QDSS_AT_ARES			199
#define GCC_QDSS_STM_ARES			200
#define GCC_QDSS_TRACECLKIN_ARES		201
#define GCC_QDSS_TSCTR_DIV2_ARES		202
#define GCC_QDSS_TSCTR_DIV3_ARES		203
#define GCC_QDSS_TSCTR_DIV4_ARES		204
#define GCC_QDSS_TSCTR_DIV8_ARES		205
#define GCC_QDSS_TSCTR_DIV16_ARES		206
#define GCC_QDSS_DAP_ARES			207
#define GCC_QDSS_APB2JTAG_ARES			208
#define GCC_QDSS_ETR_USB_ARES			209
#define GCC_QDSS_DAP_AHB_ARES			210
#define GCC_QDSS_CFG_AHB_ARES			211
#define GCC_QDSS_EUD_AT_ARES			212
#define GCC_QDSS_TS_ARES			213
#define GCC_QDSS_USB_ARES			214
#define GCC_SYS_NOC_AXI_ARES			215
#define GCC_SNOC_QOSGEN_EXTREF_ARES		216
#define GCC_CNOC_LPASS_CFG_ARES			217
#define GCC_SYS_NOC_AT_ARES			218
#define GCC_SNOC_PCNOC_AHB_ARES			219
#define GCC_SNOC_TME_ARES			220
#define GCC_SNOC_XO_DCD_ARES			221
#define GCC_SNOC_TS_ARES			222
#define GCC_ANOC0_AXI_ARES			223
#define GCC_ANOC_PCIE0_1LANE_M_ARES		224
#define GCC_ANOC_PCIE2_2LANE_M_ARES		225
#define GCC_ANOC_PCIE1_1LANE_M_ARES		226
#define GCC_ANOC_PCIE3_2LANE_M_ARES		227
#define GCC_ANOC_PCNOC_AHB_ARES			228
#define GCC_ANOC_QOSGEN_EXTREF_ARES		229
#define GCC_ANOC_XO_DCD_ARES			230
#define GCC_SNOC_XO_DBG_ARES			231
#define GCC_AGGRNOC_ATB_ARES			232
#define GCC_AGGRNOC_TS_ARES			233
#define GCC_USB0_EUD_AT_ARES			234
#define GCC_PCNOC_TIC_ARES			235
#define GCC_PCNOC_AHB_ARES			236
#define GCC_PCNOC_XO_DBG_ARES			237
#define GCC_SNOC_LPASS_ARES			238
#define GCC_PCNOC_AT_ARES			239
#define GCC_PCNOC_XO_DCD_ARES			240
#define GCC_PCNOC_TS_ARES			241
#define GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES		242
#define GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES		243
#define GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES		244
#define GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES		245
#define GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES		246
#define GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES		247
#define GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES		248
#define GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES		249
#define GCC_Q6_AXIM_RESET			250
#define GCC_Q6_AXIS_RESET			251
#define GCC_Q6_AHB_S_RESET			252
#define GCC_Q6_AHB_RESET			253
#define GCC_Q6SS_DBG_RESET			254
#define GCC_WCSS_ECAHB_RESET			255
#define GCC_WCSS_DBG_BDG_RESET			256
#define GCC_WCSS_DBG_RESET			257
#define GCC_WCSS_AXI_M_RESET			258
#define GCC_WCSS_AHB_S_RESET			259
#define GCC_WCSS_ACMT_RESET			260
#define GCC_WCSSAON_RESET			261
#define GCC_PCIE0_PIPE_RESET			262
#define GCC_PCIE0_CORE_STICKY_RESET		263
#define GCC_PCIE0_AXI_S_STICKY_RESET		264
#define GCC_PCIE0_AXI_S_RESET			265
#define GCC_PCIE0_AXI_M_STICKY_RESET		266
#define GCC_PCIE0_AXI_M_RESET			267
#define GCC_PCIE0_AUX_RESET			268
#define GCC_PCIE0_AHB_RESET			269
#define GCC_PCIE1_PIPE_RESET			270
#define GCC_PCIE1_CORE_STICKY_RESET		271
#define GCC_PCIE1_AXI_S_STICKY_RESET		272
#define GCC_PCIE1_AXI_S_RESET			273
#define GCC_PCIE1_AXI_M_STICKY_RESET		274
#define GCC_PCIE1_AXI_M_RESET			275
#define GCC_PCIE1_AUX_RESET			276
#define GCC_PCIE1_AHB_RESET			277
#define GCC_PCIE2_PIPE_RESET			278
#define GCC_PCIE2_CORE_STICKY_RESET		279
#define GCC_PCIE2_AXI_S_STICKY_RESET		280
#define GCC_PCIE2_AXI_S_RESET			281
#define GCC_PCIE2_AXI_M_STICKY_RESET		282
#define GCC_PCIE2_AXI_M_RESET			283
#define GCC_PCIE2_AUX_RESET			284
#define GCC_PCIE2_AHB_RESET			285
#define GCC_PCIE3_PIPE_RESET			286
#define GCC_PCIE3_CORE_STICKY_RESET		287
#define GCC_PCIE3_AXI_S_STICKY_RESET		288
#define GCC_PCIE3_AXI_S_RESET			289
#define GCC_PCIE3_AXI_M_STICKY_RESET		290
#define GCC_PCIE3_AXI_M_RESET			291
#define GCC_PCIE3_AUX_RESET			292
#define GCC_PCIE3_AHB_RESET			293
#define GCC_NSS_PARTIAL_RESET			294
#define GCC_UNIPHY0_XPCS_ARES			295
#define GCC_UNIPHY1_XPCS_ARES			296
#define GCC_UNIPHY2_XPCS_ARES			297
#define GCC_USB1_BCR				298
#define GCC_QUSB2_1_PHY_BCR			299

#endif