Contributors: 22
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Jani Nikula |
110 |
27.92% |
5 |
7.94% |
| José Roberto de Souza |
80 |
20.30% |
10 |
15.87% |
| Ville Syrjälä |
41 |
10.41% |
10 |
15.87% |
| Rodrigo Vivi |
31 |
7.87% |
2 |
3.17% |
| Maarten Lankhorst |
20 |
5.08% |
7 |
11.11% |
| Gwan-gyeong Mun |
17 |
4.31% |
3 |
4.76% |
| Jouni Högander |
12 |
3.05% |
5 |
7.94% |
| Animesh Manna |
11 |
2.79% |
1 |
1.59% |
| Kumar, Mahesh |
11 |
2.79% |
2 |
3.17% |
| Dhinakaran Pandiyan |
9 |
2.28% |
3 |
4.76% |
| Dave Airlie |
8 |
2.03% |
1 |
1.59% |
| Jesse Barnes |
7 |
1.78% |
2 |
3.17% |
| Chris Wilson |
6 |
1.52% |
1 |
1.59% |
| Daniel Vetter |
6 |
1.52% |
1 |
1.59% |
| Imre Deak |
5 |
1.27% |
2 |
3.17% |
| Michal Wajdeczko |
4 |
1.02% |
1 |
1.59% |
| Ander Conselvan de Oliveira |
4 |
1.02% |
2 |
3.17% |
| Shashank Sharma |
4 |
1.02% |
1 |
1.59% |
| Manasi D Navare |
3 |
0.76% |
1 |
1.59% |
| Tomeu Vizoso |
2 |
0.51% |
1 |
1.59% |
| Shubhangi Shrivastava |
2 |
0.51% |
1 |
1.59% |
| Matt Roper |
1 |
0.25% |
1 |
1.59% |
| Total |
394 |
|
63 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2019 Intel Corporation
*/
#ifndef __INTEL_PSR_H__
#define __INTEL_PSR_H__
#include <linux/types.h>
enum fb_op_origin;
struct drm_connector;
struct drm_connector_state;
struct intel_atomic_state;
struct intel_connector;
struct intel_crtc;
struct intel_crtc_state;
struct intel_display;
struct intel_dp;
struct intel_dsb;
struct intel_encoder;
struct intel_plane;
struct intel_plane_state;
#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
(intel_dp)->psr.source_panel_replay_support)
bool intel_encoder_can_psr(struct intel_encoder *encoder);
bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_psr_post_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_psr_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state);
int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
void intel_psr_invalidate(struct intel_display *display,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
void intel_psr_flush(struct intel_display *display,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
bool intel_psr_enabled(struct intel_dp *intel_dp);
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
const struct intel_crtc_state *crtc_state);
void intel_psr_pause(struct intel_dp *intel_dp);
void intel_psr_resume(struct intel_dp *intel_dp);
bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state);
bool intel_psr_link_ok(struct intel_dp *intel_dp);
void intel_psr_lock(const struct intel_crtc_state *crtc_state);
void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_psr_connector_debugfs_add(struct intel_connector *connector);
void intel_psr_debugfs_register(struct intel_display *display);
#endif /* __INTEL_PSR_H__ */