Contributors: 14
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Jani Nikula |
93 |
30.79% |
8 |
22.22% |
| Dave Airlie |
89 |
29.47% |
2 |
5.56% |
| Ville Syrjälä |
65 |
21.52% |
13 |
36.11% |
| Imre Deak |
13 |
4.30% |
2 |
5.56% |
| José Roberto de Souza |
9 |
2.98% |
1 |
2.78% |
| Suraj Kandpal |
7 |
2.32% |
1 |
2.78% |
| Ander Conselvan de Oliveira |
6 |
1.99% |
2 |
5.56% |
| Maarten Lankhorst |
4 |
1.32% |
1 |
2.78% |
| Jesse Barnes |
4 |
1.32% |
1 |
2.78% |
| Chris Wilson |
3 |
0.99% |
1 |
2.78% |
| Zhenyu Wang |
3 |
0.99% |
1 |
2.78% |
| Dhinakaran Pandiyan |
3 |
0.99% |
1 |
2.78% |
| Daniel Vetter |
2 |
0.66% |
1 |
2.78% |
| Tvrtko A. Ursulin |
1 |
0.33% |
1 |
2.78% |
| Total |
302 |
|
36 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2020 Intel Corporation
*/
#ifndef _INTEL_DPLL_H_
#define _INTEL_DPLL_H_
#include <linux/types.h>
enum pipe;
struct dpll;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_display;
struct intel_dpll_hw_state;
void intel_dpll_init_clock_hook(struct intel_display *display);
int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
struct intel_dpll_hw_state *dpll_hw_state);
void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
void chv_compute_dpll(struct intel_crtc_state *crtc_state);
int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,
const struct dpll *dpll);
void vlv_force_pll_off(struct intel_display *display, enum pipe pipe);
void chv_enable_pll(const struct intel_crtc_state *crtc_state);
void chv_disable_pll(struct intel_display *display, enum pipe pipe);
void vlv_enable_pll(const struct intel_crtc_state *crtc_state);
void vlv_disable_pll(struct intel_display *display, enum pipe pipe);
void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);
void i9xx_disable_pll(const struct intel_crtc_state *crtc_state);
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
void assert_pll_enabled(struct intel_display *display, enum pipe pipe);
void assert_pll_disabled(struct intel_display *display, enum pipe pipe);
#endif