| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Ben Skeggs | 2417 | 99.96% | 5 | 83.33% |
| Dave Airlie | 1 | 0.04% | 1 | 16.67% |
| Total | 2418 | 6 |
/* SPDX-License-Identifier: MIT */ /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ #ifndef __NVRM_DISP_H__ #define __NVRM_DISP_H__ #include <nvrm/nvtypes.h> /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); NvU32 instMemAddrSpace; NvU32 instMemCpuCacheAttr; } NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; #define NV_MEMORY_WRITECOMBINED 2 #define NV04_DISPLAY_COMMON (0x00000073) #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { NvU32 feHwSysCap; NvU32 windowPresentMask; NvBool bFbRemapperEnabled; NvU32 numHeads; NvBool bPrimaryVga; NvU32 i2cPort; NvU32 internalDispActiveMask; } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; #define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ #define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { NvU32 status; NvU16 backLightDataSize; NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; } NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS { NvU32 subDeviceInstance; } NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS; #define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS { NvU32 subDeviceInstance; NvU32 flags; NvU32 numHeads; } NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS; #define NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK (0x730287U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS { NvU32 subDeviceInstance; NvU32 headMask; } NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS; #define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS { NvU32 subDeviceInstance; NvU32 displayMask; NvU32 displayMaskDDC; } NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS; #define NV0073_CTRL_MAX_CONNECTORS 4U #define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 flags; NvU32 DDCPartners; NvU32 count; struct { NvU32 index; NvU32 type; NvU32 location; } data[NV0073_CTRL_MAX_CONNECTORS]; NvU32 platform; } NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS; #define NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO (0x73028bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 index; NvU32 type; NvU32 protocol; NvU32 ditherType; NvU32 ditherAlgo; NvU32 location; NvU32 rootPortId; NvU32 dcbIndex; NV_DECLARE_ALIGNED(NvU64 vbiosAddress, 8); NvBool bIsLitByVbios; NvBool bIsDispDynamic; } NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS; #define NV0073_CTRL_SPECIFIC_OR_TYPE_NONE (0x00000000U) #define NV0073_CTRL_SPECIFIC_OR_TYPE_DAC (0x00000001U) #define NV0073_CTRL_SPECIFIC_OR_TYPE_SOR (0x00000002U) #define NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR (0x00000003U) #define NV0073_CTRL_SPECIFIC_OR_TYPE_DSI (0x00000005U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT (0x00000000U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS (0x00000005U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A (0x00000008U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B (0x00000009U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DSI (0x00000010U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI (0x00000011U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC (0x00000000U) #define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN (0xFFFFFFFFU) #define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS { NvBool bDscSupported; NvU32 encoderColorFormatMask; NvU32 lineBufferSizeKB; NvU32 rateBufferSizeKB; NvU32 bitsPerPixelPrecision; NvU32 maxNumHztSlices; NvU32 lineBufferBitDepth; } NV0073_CTRL_CMD_DSC_CAP_PARAMS; typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { NvU32 subDeviceInstance; NvU32 sorIndex; NvU32 maxLinkRate; NvU32 dpVersionsSupported; NvU32 UHBRSupported; NvBool bIsMultistreamSupported; NvBool bIsSCEnabled; NvBool bHasIncreasedWatermarkLimits; NvBool bIsPC2Disabled; NvBool isSingleHeadMSTSupported; NvBool bFECSupported; NvBool bIsTrainPhyRepeater; NvBool bOverrideLinkBw; NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; } NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; #define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) #define NV2080_NOTIFIERS_HOTPLUG (1) typedef struct { NvU32 plugDisplayMask; NvU32 unplugDisplayMask; } Nv2080HotplugNotification; #define NV2080_NOTIFIERS_DP_IRQ (7) typedef struct Nv2080DpIrqNotificationRec { NvU32 displayId; } Nv2080DpIrqNotification; #define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730122U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS { NvU32 subDeviceInstance; NvU32 flags; NvU32 displayMask; NvU32 retryTimeMs; } NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS; #define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 flags; NvU32 flags2; } NV0073_CTRL_DFP_GET_INFO_PARAMS; #define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) #define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) #define NV0073_CTRL_DFP_FLAGS_LANE 5:3 #define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) #define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) #define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) #define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 #define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) #define NV0073_CTRL_DFP_FLAGS_LINK 21:20 #define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x730126U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS { NvU32 subDeviceInstance; NvU32 head; NvU32 flags; NvU32 displayId; } NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS; typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { NvU32 displayMask; NvU32 sorType; } NV0073_CTRL_DFP_ASSIGN_SOR_INFO; #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU8 sorExcludeMask; NvU32 slaveDisplayId; NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig; NvBool bIs2Head1Or; NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; NvU8 reservedSorMask; NvU32 flags; } NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS; #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U) #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U) #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U) #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 brightness; NvBool bUncalibrated; } NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; #define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 numELDSize; NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; NvU32 maxFreqSupported; NvU32 ctrl; NvU32 deviceEntry; } NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS; #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U) #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U) #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U) #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U) #define NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES 2048U #define NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 (0x730245U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 bufferSize; NvU32 flags; NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; } NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS; #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE (0x730273U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS { NvU8 subDeviceInstance; NvU32 displayId; NvU8 enable; } NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS; #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 caps; } NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS; #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED 0:0 #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_FALSE (0x00000000U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_TRUE (0x00000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED 1:1 #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_FALSE (0x00000000U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_TRUE (0x00000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED 2:2 #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_FALSE (0x00000000U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_TRUE (0x00000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED 5:3 #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED 6:6 #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_FALSE (0x00000000U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_TRUE (0x00000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED 9:7 #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) #define NV0073_CTRL_SET_OD_MAX_PACKET_SIZE 36U #define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET (0x730288U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 transmitControl; NvU32 packetSize; NvU32 targetHead; NvBool bUsePsrHeadforSdp; NvU8 aPacket[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; } NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS; #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE 0:0 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME 1:1 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME 2:2 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK 3:3 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE 4:4 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_DISABLE (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_ENABLE (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT 5:5 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY 6:6 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING 7:7 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE 9:8 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME0 (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME1 (0x0000001U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE 31:31 #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO (0x0000000U) #define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES (0x0000001U) #define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM (0x730275U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS { NvU8 subDeviceInstance; NvU32 displayId; NvU8 mute; } NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS; #define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U #define NV0073_CTRL_CMD_DP_AUXCH_CTRL (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvBool bAddrOnly; NvU32 cmd; NvU32 addr; NvU8 data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE]; NvU32 size; NvU32 replyType; NvU32 retryTimeMs; } NV0073_CTRL_DP_AUXCH_CTRL_PARAMS; #define NV0073_CTRL_DP_AUXCH_CMD_TYPE 3:3 #define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C (0x00000000U) #define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX (0x00000001U) #define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT 2:2 #define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE (0x00000000U) #define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE (0x00000001U) #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE 1:0 #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE (0x00000000U) #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ (0x00000001U) #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS (0x00000002U) #define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { // In NvU32 subDeviceInstance; NvU32 displayId; NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; // Out NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; NvU8 linkBwCount; } NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; #define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_DP_CTRL_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 cmd; NvU32 data; NvU32 err; NvU32 retryTimeMs; NvU32 eightLaneDpcdBaseAddr; } NV0073_CTRL_DP_CTRL_PARAMS; #define NV0073_CTRL_DP_CMD_SET_LANE_COUNT 0:0 #define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_SET_LINK_BW 1:1 #define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD 2:2 #define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_UNUSED 3:3 #define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE 4:4 #define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM (0x00000000U) #define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM (0x00000001U) #define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING 5:5 #define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO (0x00000000U) #define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES (0x00000001U) #define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING 6:6 #define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO (0x00000000U) #define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES (0x00000001U) #define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING 7:7 #define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING 8:8 #define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT (0x00000000U) #define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE (0x00000001U) #define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING 9:9 #define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) #define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) #define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED 10:10 #define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000U) #define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001U) #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING 12:11 #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) #define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER 13:13 #define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO (0x00000000U) #define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES (0x00000001U) #define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG 14:14 #define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_ENABLE_FEC 15:15 #define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST 29:29 #define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO (0x00000000U) #define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES (0x00000001U) #define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE 30:30 #define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG 31:31 #define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE (0x00000000U) #define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE (0x00000001U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE 3:0 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN (0x00000000U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK (0x00000002U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN (0x00000003U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE (0x00000004U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK (0x00000005U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR (0x00000006U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO (0x00000007U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO (0x00000008U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK (0x00000009U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK (0x00000000U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING (0x80000001U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR (0x80000002U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR (0x80000003U) #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR (0x80000004U) #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT 4:0 #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 (0x00000000U) #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 (0x00000001U) #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 (0x00000002U) #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 (0x00000004U) #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 (0x00000008U) #define NV0073_CTRL_DP_DATA_SET_LINK_BW 15:8 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS (0x00000006U) #define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS (0x00000008U) #define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS (0x00000009U) #define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS (0x0000000AU) #define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS (0x0000000CU) #define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS (0x00000010U) #define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS (0x00000014U) #define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS (0x0000001EU) #define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING 18:18 #define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO (0x00000000U) #define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES (0x00000001U) #define NV0073_CTRL_DP_DATA_TARGET 22:19 #define NV0073_CTRL_DP_DATA_TARGET_SINK (0x00000000U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0 (0x00000001U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1 (0x00000002U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2 (0x00000003U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3 (0x00000004U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4 (0x00000005U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5 (0x00000006U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6 (0x00000007U) #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7 (0x00000008U) #define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_MAX_LANES 8U typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 numLanes; NvU32 data[NV0073_CTRL_MAX_LANES]; } NV0073_CTRL_DP_LANE_DATA_PARAMS; #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS 1:0 #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE (0x00000000U) #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 (0x00000001U) #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 (0x00000002U) #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 (0x00000003U) #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT 3:2 #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U) #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U) #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U) #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U) #define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 preferredDisplayId; NvBool force; NvBool useBFM; NvU32 displayIdAssigned; NvU32 allDisplayMask; } NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS; #define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; } NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS; #define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { NvU32 subDeviceInstance; NvU32 head; NvU32 sorIndex; NvU32 dpLink; NvBool bEnableOverride; NvBool bMST; NvU32 singleHeadMultistreamMode; NvU32 hBlankSym; NvU32 vBlankSym; NvU32 colorFormat; NvBool bEnableTwoHeadOneOr; struct { NvU32 slotStart; NvU32 slotEnd; NvU32 PBN; NvU32 Timeslice; NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT NvU32 singleHeadMSTPipeline; NvBool bEnableAudioOverRightPanel; } MST; struct { NvBool bEnhancedFraming; NvU32 tuSize; NvU32 waterMark; NvU32 actualPclkHz; // deprecated -Use MvidWarParams NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams NvBool bEnableAudioOverRightPanel; struct { NvU32 activeCnt; NvU32 activeFrac; NvU32 activePolarity; NvBool mvidWarEnabled; struct { NvU32 actualPclkHz; NvU32 linkClkFreqHz; } MvidWarParams; } Legacy; } SST; } NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS; #define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvBool enable; } NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS; #define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 mute; } NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS; #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { NvU32 addressSpace; NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); NV_DECLARE_ALIGNED(NvU64 limit, 8); NvU32 cacheSnoop; NvU32 hclass; NvU32 channelInstance; NvBool valid; } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; #define ADDR_SYSMEM (1) // System memory (PCI) #define ADDR_FBMEM 2 // Frame buffer memory space typedef struct { NvV32 channelInstance; // One of the n channel instances of a given channel type. // All PIO channels have two instances (one per head). NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors. NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel } NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS; typedef struct { NvV32 channelInstance; // One of the n channel instances of a given channel type. // Note that core channel has only one instance // while all others have two (one per head). NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications NvU32 offset; // Initial offset for put/get, usually zero. NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs NvU32 flags; #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 #define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 } NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; #endif
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