Contributors: 10
Author Tokens Token Proportion Commits Commit Proportion
Matthew Brost 145 44.07% 2 14.29%
Tejas Upadhyay 92 27.96% 1 7.14%
Rodrigo Vivi 25 7.60% 1 7.14%
Dominik Grzegorzek 24 7.29% 2 14.29%
Niranjana Vishwanathapura 13 3.95% 1 7.14%
Nirmoy Das 9 2.74% 1 7.14%
José Roberto de Souza 8 2.43% 1 7.14%
Zhanjun Dong 5 1.52% 1 7.14%
Lucas De Marchi 5 1.52% 3 21.43%
Umesh Nerlige Ramappa 3 0.91% 1 7.14%
Total 329 14 


/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2021 Intel Corporation
 */

#ifndef _XE_HW_ENGINE_H_
#define _XE_HW_ENGINE_H_

#include "xe_hw_engine_types.h"

struct drm_printer;
struct drm_xe_engine_class_instance;
struct xe_device;
struct xe_exec_queue;

#ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MIN
#define XE_HW_ENGINE_JOB_TIMEOUT_MIN CONFIG_DRM_XE_JOB_TIMEOUT_MIN
#else
#define XE_HW_ENGINE_JOB_TIMEOUT_MIN 1
#endif
#ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MAX
#define XE_HW_ENGINE_JOB_TIMEOUT_MAX CONFIG_DRM_XE_JOB_TIMEOUT_MAX
#else
#define XE_HW_ENGINE_JOB_TIMEOUT_MAX (10 * 1000)
#endif
#ifdef CONFIG_DRM_XE_TIMESLICE_MIN
#define XE_HW_ENGINE_TIMESLICE_MIN CONFIG_DRM_XE_TIMESLICE_MIN
#else
#define XE_HW_ENGINE_TIMESLICE_MIN 1
#endif
#ifdef CONFIG_DRM_XE_TIMESLICE_MAX
#define XE_HW_ENGINE_TIMESLICE_MAX CONFIG_DRM_XE_TIMESLICE_MAX
#else
#define XE_HW_ENGINE_TIMESLICE_MAX (10 * 1000 * 1000)
#endif
#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT
#define XE_HW_ENGINE_PREEMPT_TIMEOUT CONFIG_DRM_XE_PREEMPT_TIMEOUT
#else
#define XE_HW_ENGINE_PREEMPT_TIMEOUT (640 * 1000)
#endif
#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN
#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN
#else
#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN 1
#endif
#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX
#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX
#else
#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX (10 * 1000 * 1000)
#endif

int xe_hw_engines_init_early(struct xe_gt *gt);
int xe_hw_engines_init(struct xe_gt *gt);
void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec);
void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);
u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
				enum xe_engine_class engine_class);
struct xe_hw_engine_snapshot *
xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe, struct xe_exec_queue *q);
void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot);
void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p);
void xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe);

bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe);

struct xe_hw_engine *
xe_hw_engine_lookup(struct xe_device *xe,
		    struct drm_xe_engine_class_instance eci);

static inline bool xe_hw_engine_is_valid(struct xe_hw_engine *hwe)
{
	return hwe->name;
}

const char *xe_hw_engine_class_to_str(enum xe_engine_class class);
u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe);
enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe);

void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val);
u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);

#endif