Contributors: 1
Author Tokens Token Proportion Commits Commit Proportion
Andre Przywara 727 100.00% 1 100.00%
Total 727 1 


/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
 * Copyright (C) 2024 Arm Ltd.
 */

#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_
#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_

#define CLK_PLL_DDR0		0
#define CLK_PLL_PERIPH0_4X	1
#define CLK_PLL_PERIPH0_2X	2
#define CLK_PLL_PERIPH0_800M	3
#define CLK_PLL_PERIPH0_480M	4
#define CLK_PLL_PERIPH0_600M	5
#define CLK_PLL_PERIPH0_400M	6
#define CLK_PLL_PERIPH0_300M	7
#define CLK_PLL_PERIPH0_200M	8
#define CLK_PLL_PERIPH0_160M	9
#define CLK_PLL_PERIPH0_150M	10
#define CLK_PLL_PERIPH1_4X	11
#define CLK_PLL_PERIPH1_2X	12
#define CLK_PLL_PERIPH1_800M	13
#define CLK_PLL_PERIPH1_480M	14
#define CLK_PLL_PERIPH1_600M	15
#define CLK_PLL_PERIPH1_400M	16
#define CLK_PLL_PERIPH1_300M	17
#define CLK_PLL_PERIPH1_200M	18
#define CLK_PLL_PERIPH1_160M	19
#define CLK_PLL_PERIPH1_150M	20
#define CLK_PLL_GPU		21
#define CLK_PLL_VIDEO0_8X	22
#define CLK_PLL_VIDEO0_4X	23
#define CLK_PLL_VIDEO0_3X	24
#define CLK_PLL_VIDEO1_8X	25
#define CLK_PLL_VIDEO1_4X	26
#define CLK_PLL_VIDEO1_3X	27
#define CLK_PLL_VIDEO2_8X	28
#define CLK_PLL_VIDEO2_4X	29
#define CLK_PLL_VIDEO2_3X	30
#define CLK_PLL_VIDEO3_8X	31
#define CLK_PLL_VIDEO3_4X	32
#define CLK_PLL_VIDEO3_3X	33
#define CLK_PLL_VE		34
#define CLK_PLL_AUDIO0_4X	35
#define CLK_PLL_AUDIO0_2X	36
#define CLK_PLL_AUDIO0		37
#define CLK_PLL_NPU_4X		38
#define CLK_PLL_NPU_2X		39
#define CLK_PLL_NPU		40
#define CLK_AHB			41
#define CLK_APB0		42
#define CLK_APB1		43
#define CLK_MBUS		44
#define CLK_DE			45
#define CLK_BUS_DE		46
#define CLK_DI			47
#define CLK_BUS_DI		48
#define CLK_G2D			49
#define CLK_BUS_G2D		50
#define CLK_GPU			51
#define CLK_BUS_GPU		52
#define CLK_CE			53
#define CLK_BUS_CE		54
#define CLK_BUS_CE_SYS		55
#define CLK_VE			56
#define CLK_BUS_VE		57
#define CLK_BUS_DMA		58
#define CLK_BUS_MSGBOX		59
#define CLK_BUS_SPINLOCK	60
#define CLK_HSTIMER0		61
#define CLK_HSTIMER1		62
#define CLK_HSTIMER2		63
#define CLK_HSTIMER3		64
#define CLK_HSTIMER4		65
#define CLK_HSTIMER5		66
#define CLK_BUS_HSTIMER		67
#define CLK_BUS_DBG		68
#define CLK_BUS_PWM0		69
#define CLK_BUS_PWM1		70
#define CLK_IOMMU		71
#define CLK_BUS_IOMMU		72
#define CLK_DRAM		73
#define CLK_MBUS_DMA		74
#define CLK_MBUS_VE		75
#define CLK_MBUS_CE		76
#define CLK_MBUS_CSI		77
#define CLK_MBUS_ISP		78
#define CLK_MBUS_EMAC1		79
#define CLK_BUS_DRAM		80
#define CLK_NAND0		81
#define CLK_NAND1		82
#define CLK_BUS_NAND		83
#define CLK_MMC0		84
#define CLK_MMC1		85
#define CLK_MMC2		86
#define CLK_BUS_SYSDAP		87
#define CLK_BUS_MMC0		88
#define CLK_BUS_MMC1		89
#define CLK_BUS_MMC2		90
#define CLK_BUS_UART0		91
#define CLK_BUS_UART1		92
#define CLK_BUS_UART2		93
#define CLK_BUS_UART3		94
#define CLK_BUS_UART4		95
#define CLK_BUS_UART5		96
#define CLK_BUS_UART6		97
#define CLK_BUS_UART7		98
#define CLK_BUS_I2C0		99
#define CLK_BUS_I2C1		100
#define CLK_BUS_I2C2		101
#define CLK_BUS_I2C3		102
#define CLK_BUS_I2C4		103
#define CLK_BUS_I2C5		104
#define CLK_BUS_CAN		105
#define CLK_SPI0		106
#define CLK_SPI1		107
#define CLK_SPI2		108
#define CLK_SPIFC		109
#define CLK_BUS_SPI0		110
#define CLK_BUS_SPI1		111
#define CLK_BUS_SPI2		112
#define CLK_BUS_SPIFC		113
#define CLK_EMAC0_25M		114
#define CLK_EMAC1_25M		115
#define CLK_BUS_EMAC0		116
#define CLK_BUS_EMAC1		117
#define CLK_IR_RX		118
#define CLK_BUS_IR_RX		119
#define CLK_IR_TX		120
#define CLK_BUS_IR_TX		121
#define CLK_GPADC0		122
#define CLK_GPADC1		123
#define CLK_BUS_GPADC0		124
#define CLK_BUS_GPADC1		125
#define CLK_BUS_THS		126
#define CLK_USB_OHCI0		127
#define CLK_USB_OHCI1		128
#define CLK_BUS_OHCI0		129
#define CLK_BUS_OHCI1		130
#define CLK_BUS_EHCI0		131
#define CLK_BUS_EHCI1		132
#define CLK_BUS_OTG		133
#define CLK_BUS_LRADC		134
#define CLK_PCIE_AUX		135
#define CLK_BUS_DISPLAY0_TOP	136
#define CLK_BUS_DISPLAY1_TOP	137
#define CLK_HDMI_24M		138
#define CLK_HDMI_CEC_32K	139
#define CLK_HDMI_CEC		140
#define CLK_BUS_HDMI		141
#define CLK_MIPI_DSI0		142
#define CLK_MIPI_DSI1		143
#define CLK_BUS_MIPI_DSI0	144
#define CLK_BUS_MIPI_DSI1	145
#define CLK_TCON_LCD0		146
#define CLK_TCON_LCD1		147
#define CLK_TCON_LCD2		148
#define CLK_COMBOPHY_DSI0	149
#define CLK_COMBOPHY_DSI1	150
#define CLK_BUS_TCON_LCD0	151
#define CLK_BUS_TCON_LCD1	152
#define CLK_BUS_TCON_LCD2	153
#define CLK_TCON_TV0		154
#define CLK_TCON_TV1		155
#define CLK_BUS_TCON_TV0	156
#define CLK_BUS_TCON_TV1	157
#define CLK_EDP			158
#define CLK_BUS_EDP		159
#define CLK_LEDC		160
#define CLK_BUS_LEDC		161
#define CLK_CSI_TOP		162
#define CLK_CSI_MCLK0		163
#define CLK_CSI_MCLK1		164
#define CLK_CSI_MCLK2		165
#define CLK_CSI_MCLK3		166
#define CLK_BUS_CSI		167
#define CLK_ISP			168
#define CLK_DSP			169
#define CLK_FANOUT_24M		170
#define CLK_FANOUT_12M		171
#define CLK_FANOUT_16M		172
#define CLK_FANOUT_25M		173
#define CLK_FANOUT_27M		174
#define CLK_FANOUT_PCLK		175
#define CLK_FANOUT0		176
#define CLK_FANOUT1		177
#define CLK_FANOUT2		178

#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */