Contributors: 10
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Jani Nikula |
77 |
34.68% |
6 |
37.50% |
| Chris Wilson |
51 |
22.97% |
2 |
12.50% |
| Imre Deak |
36 |
16.22% |
1 |
6.25% |
| Dale B Stimson |
28 |
12.61% |
1 |
6.25% |
| Ashutosh Dixit |
14 |
6.31% |
1 |
6.25% |
| Ville Syrjälä |
8 |
3.60% |
1 |
6.25% |
| Matt Roper |
3 |
1.35% |
1 |
6.25% |
| Badal Nilawar |
2 |
0.90% |
1 |
6.25% |
| Clint Taylor |
2 |
0.90% |
1 |
6.25% |
| Sean Paul |
1 |
0.45% |
1 |
6.25% |
| Total |
222 |
|
16 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2013-2021 Intel Corporation
*/
#ifndef _INTEL_PCODE_H_
#define _INTEL_PCODE_H_
#include <linux/types.h>
struct drm_device;
struct intel_uncore;
int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, int timeout_ms);
#define snb_pcode_write(uncore, mbox, val) \
snb_pcode_write_timeout((uncore), (mbox), (val), 1)
int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
int intel_pcode_init(struct intel_uncore *uncore);
/*
* Helpers for dGfx PCODE mailbox command formatting
*/
int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
/* Helpers with drm device */
int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
#define intel_pcode_write(drm, mbox, val) \
intel_pcode_write_timeout((drm), (mbox), (val), 1)
int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
#endif /* _INTEL_PCODE_H */