Contributors: 5
Author Tokens Token Proportion Commits Commit Proportion
Jacob E Keller 172 81.90% 1 16.67%
Anirudh Venkataramanan 23 10.95% 2 33.33%
Sergey Temerkhanov 7 3.33% 1 16.67%
Karol Kolacinski 4 1.90% 1 16.67%
Grzegorz Nitka 4 1.90% 1 16.67%
Total 210 6 


/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2021, Intel Corporation. */

#ifndef _ICE_SBQ_CMD_H_
#define _ICE_SBQ_CMD_H_

/* This header file defines the Sideband Queue commands, error codes and
 * descriptor format. It is shared between Firmware and Software.
 */

/* Sideband Queue command structure and opcodes */
enum ice_sbq_opc {
	/* Sideband Queue commands */
	ice_sbq_opc_neigh_dev_req			= 0x0C00,
	ice_sbq_opc_neigh_dev_ev			= 0x0C01
};

/* Sideband Queue descriptor. Indirect command
 * and non posted
 */
struct ice_sbq_cmd_desc {
	__le16 flags;
	__le16 opcode;
	__le16 datalen;
	__le16 cmd_retval;

	/* Opaque message data */
	__le32 cookie_high;
	__le32 cookie_low;

	union {
		__le16 cmd_len;
		__le16 cmpl_len;
	} param0;

	u8 reserved[6];
	__le32 addr_high;
	__le32 addr_low;
};

struct ice_sbq_evt_desc {
	__le16 flags;
	__le16 opcode;
	__le16 datalen;
	__le16 cmd_retval;
	u8 data[24];
};

enum ice_sbq_dev_id {
	ice_sbq_dev_phy_0	= 0x02,
	ice_sbq_dev_cgu		= 0x06,
	ice_sbq_dev_phy_0_peer	= 0x0D,
	ice_sbq_dev_cgu_peer	= 0x0F,
};

enum ice_sbq_msg_opcode {
	ice_sbq_msg_rd	= 0x00,
	ice_sbq_msg_wr	= 0x01
};

#define ICE_SBQ_MSG_FLAGS	0x40
#define ICE_SBQ_MSG_SBE_FBE	0x0F

struct ice_sbq_msg_req {
	u8 dest_dev;
	u8 src_dev;
	u8 opcode;
	u8 flags;
	u8 sbe_fbe;
	u8 func_id;
	__le16 msg_addr_low;
	__le32 msg_addr_high;
	__le32 data;
};

struct ice_sbq_msg_cmpl {
	u8 dest_dev;
	u8 src_dev;
	u8 opcode;
	u8 flags;
	__le32 data;
};

/* Internal struct */
struct ice_sbq_msg_input {
	u8 dest_dev;
	u8 opcode;
	u16 msg_addr_low;
	u32 msg_addr_high;
	u32 data;
};
#endif /* _ICE_SBQ_CMD_H_ */