Contributors: 5
Author Tokens Token Proportion Commits Commit Proportion
Aaron Kling 292 49.91% 1 20.00%
Thierry Reding 132 22.56% 1 20.00%
Dmitry Osipenko 120 20.51% 1 20.00%
Nicolin Chen 40 6.84% 1 20.00%
Greg Kroah-Hartman 1 0.17% 1 20.00%
Total 585 5 


/* SPDX-License-Identifier: GPL-2.0 */
#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
#define DT_BINDINGS_MEMORY_TEGRA210_MC_H

#define TEGRA_SWGROUP_PTC	0
#define TEGRA_SWGROUP_DC	1
#define TEGRA_SWGROUP_DCB	2
#define TEGRA_SWGROUP_AFI	3
#define TEGRA_SWGROUP_AVPC	4
#define TEGRA_SWGROUP_HDA	5
#define TEGRA_SWGROUP_HC	6
#define TEGRA_SWGROUP_NVENC	7
#define TEGRA_SWGROUP_PPCS	8
#define TEGRA_SWGROUP_SATA	9
#define TEGRA_SWGROUP_MPCORE	10
#define TEGRA_SWGROUP_ISP2	11
#define TEGRA_SWGROUP_XUSB_HOST	12
#define TEGRA_SWGROUP_XUSB_DEV	13
#define TEGRA_SWGROUP_ISP2B	14
#define TEGRA_SWGROUP_TSEC	15
#define TEGRA_SWGROUP_A9AVP	16
#define TEGRA_SWGROUP_GPU	17
#define TEGRA_SWGROUP_SDMMC1A	18
#define TEGRA_SWGROUP_SDMMC2A	19
#define TEGRA_SWGROUP_SDMMC3A	20
#define TEGRA_SWGROUP_SDMMC4A	21
#define TEGRA_SWGROUP_VIC	22
#define TEGRA_SWGROUP_VI	23
#define TEGRA_SWGROUP_NVDEC	24
#define TEGRA_SWGROUP_APE	25
#define TEGRA_SWGROUP_NVJPG	26
#define TEGRA_SWGROUP_SE	27
#define TEGRA_SWGROUP_AXIAP	28
#define TEGRA_SWGROUP_ETR	29
#define TEGRA_SWGROUP_TSECB	30
#define TEGRA_SWGROUP_NV	31
#define TEGRA_SWGROUP_NV2	32
#define TEGRA_SWGROUP_PPCS1	33
#define TEGRA_SWGROUP_DC1	34
#define TEGRA_SWGROUP_PPCS2	35
#define TEGRA_SWGROUP_HC1	36
#define TEGRA_SWGROUP_SE1	37
#define TEGRA_SWGROUP_TSEC1	38
#define TEGRA_SWGROUP_TSECB1	39
#define TEGRA_SWGROUP_NVDEC1	40

#define TEGRA210_MC_RESET_AFI		0
#define TEGRA210_MC_RESET_AVPC		1
#define TEGRA210_MC_RESET_DC		2
#define TEGRA210_MC_RESET_DCB		3
#define TEGRA210_MC_RESET_HC		4
#define TEGRA210_MC_RESET_HDA		5
#define TEGRA210_MC_RESET_ISP2		6
#define TEGRA210_MC_RESET_MPCORE	7
#define TEGRA210_MC_RESET_NVENC		8
#define TEGRA210_MC_RESET_PPCS		9
#define TEGRA210_MC_RESET_SATA		10
#define TEGRA210_MC_RESET_VI		11
#define TEGRA210_MC_RESET_VIC		12
#define TEGRA210_MC_RESET_XUSB_HOST	13
#define TEGRA210_MC_RESET_XUSB_DEV	14
#define TEGRA210_MC_RESET_A9AVP		15
#define TEGRA210_MC_RESET_TSEC		16
#define TEGRA210_MC_RESET_SDMMC1	17
#define TEGRA210_MC_RESET_SDMMC2	18
#define TEGRA210_MC_RESET_SDMMC3	19
#define TEGRA210_MC_RESET_SDMMC4	20
#define TEGRA210_MC_RESET_ISP2B		21
#define TEGRA210_MC_RESET_GPU		22
#define TEGRA210_MC_RESET_NVDEC		23
#define TEGRA210_MC_RESET_APE		24
#define TEGRA210_MC_RESET_SE		25
#define TEGRA210_MC_RESET_NVJPG		26
#define TEGRA210_MC_RESET_AXIAP		27
#define TEGRA210_MC_RESET_ETR		28
#define TEGRA210_MC_RESET_TSECB		29

#define TEGRA210_MC_PTCR		0
#define TEGRA210_MC_DISPLAY0A		1
#define TEGRA210_MC_DISPLAY0AB		2
#define TEGRA210_MC_DISPLAY0B		3
#define TEGRA210_MC_DISPLAY0BB		4
#define TEGRA210_MC_DISPLAY0C		5
#define TEGRA210_MC_DISPLAY0CB		6
#define TEGRA210_MC_AFIR		14
#define TEGRA210_MC_AVPCARM7R		15
#define TEGRA210_MC_DISPLAYHC		16
#define TEGRA210_MC_DISPLAYHCB		17
#define TEGRA210_MC_HDAR		21
#define TEGRA210_MC_HOST1XDMAR		22
#define TEGRA210_MC_HOST1XR		23
#define TEGRA210_MC_NVENCSRD		28
#define TEGRA210_MC_PPCSAHBDMAR		29
#define TEGRA210_MC_PPCSAHBSLVR		30
#define TEGRA210_MC_SATAR		31
#define TEGRA210_MC_MPCORER		39
#define TEGRA210_MC_NVENCSWR		43
#define TEGRA210_MC_AFIW		49
#define TEGRA210_MC_AVPCARM7W		50
#define TEGRA210_MC_HDAW		53
#define TEGRA210_MC_HOST1XW		54
#define TEGRA210_MC_MPCOREW		57
#define TEGRA210_MC_PPCSAHBDMAW		59
#define TEGRA210_MC_PPCSAHBSLVW		60
#define TEGRA210_MC_SATAW		61
#define TEGRA210_MC_ISPRA		68
#define TEGRA210_MC_ISPWA		70
#define TEGRA210_MC_ISPWB		71
#define TEGRA210_MC_XUSB_HOSTR		74
#define TEGRA210_MC_XUSB_HOSTW		75
#define TEGRA210_MC_XUSB_DEVR		76
#define TEGRA210_MC_XUSB_DEVW		77
#define TEGRA210_MC_ISPRAB		78
#define TEGRA210_MC_ISPWAB		80
#define TEGRA210_MC_ISPWBB		81
#define TEGRA210_MC_TSECSRD		84
#define TEGRA210_MC_TSECSWR		85
#define TEGRA210_MC_A9AVPSCR		86
#define TEGRA210_MC_A9AVPSCW		87
#define TEGRA210_MC_GPUSRD		88
#define TEGRA210_MC_GPUSWR		89
#define TEGRA210_MC_DISPLAYT		90
#define TEGRA210_MC_SDMMCRA		96
#define TEGRA210_MC_SDMMCRAA		97
#define TEGRA210_MC_SDMMCR		98
#define TEGRA210_MC_SDMMCRAB		99
#define TEGRA210_MC_SDMMCWA		100
#define TEGRA210_MC_SDMMCWAA		101
#define TEGRA210_MC_SDMMCW		102
#define TEGRA210_MC_SDMMCWAB		103
#define TEGRA210_MC_VICSRD		108
#define TEGRA210_MC_VICSWR		109
#define TEGRA210_MC_VIW			114
#define TEGRA210_MC_DISPLAYD		115
#define TEGRA210_MC_NVDECSRD		120
#define TEGRA210_MC_NVDECSWR		121
#define TEGRA210_MC_APER		122
#define TEGRA210_MC_APEW		123
#define TEGRA210_MC_NVJPGRD		126
#define TEGRA210_MC_NVJPGWR		127
#define TEGRA210_MC_SESRD		128
#define TEGRA210_MC_SESWR		129
#define TEGRA210_MC_AXIAPR		130
#define TEGRA210_MC_AXIAPW		131
#define TEGRA210_MC_ETRR		132
#define TEGRA210_MC_ETRW		133
#define TEGRA210_MC_TSECSRDB		134
#define TEGRA210_MC_TSECSWRB		135
#define TEGRA210_MC_GPUSRD2		136
#define TEGRA210_MC_GPUSWR2		137

#endif