Contributors: 31
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Venkatesh Pallipadi |
131 |
18.88% |
1 |
2.00% |
| Fenghua Yu |
96 |
13.83% |
4 |
8.00% |
| Borislav Petkov |
78 |
11.24% |
4 |
8.00% |
| Babu Moger |
48 |
6.92% |
4 |
8.00% |
| Sandipan Das |
36 |
5.19% |
3 |
6.00% |
| Sean Christopherson |
31 |
4.47% |
1 |
2.00% |
| H. Peter Anvin |
28 |
4.03% |
1 |
2.00% |
| Perry Yuan |
27 |
3.89% |
3 |
6.00% |
| Suresh B. Siddha |
20 |
2.88% |
2 |
4.00% |
| Pawan Gupta |
19 |
2.74% |
1 |
2.00% |
| Tony Luck |
18 |
2.59% |
1 |
2.00% |
| He Chen |
16 |
2.31% |
2 |
4.00% |
| Sherry Hurwitz |
13 |
1.87% |
1 |
2.00% |
| Kai Huang |
12 |
1.73% |
1 |
2.00% |
| Tom Lendacky |
12 |
1.73% |
1 |
2.00% |
| Vikas Shivappa |
12 |
1.73% |
1 |
2.00% |
| Naveen N Rao |
12 |
1.73% |
1 |
2.00% |
| Chang S. Bae |
12 |
1.73% |
1 |
2.00% |
| Thomas Renninger |
11 |
1.59% |
1 |
2.00% |
| Andi Kleen |
11 |
1.59% |
2 |
4.00% |
| Piotr Luc |
10 |
1.44% |
1 |
2.00% |
| Alexander Shishkin |
8 |
1.15% |
1 |
2.00% |
| Xin Li (Intel) |
7 |
1.01% |
2 |
4.00% |
| Daniel Sneddon |
5 |
0.72% |
1 |
2.00% |
| Elena Reshetova |
5 |
0.72% |
1 |
2.00% |
| Thomas Gleixner |
5 |
0.72% |
2 |
4.00% |
| Jacob Shin |
4 |
0.58% |
1 |
2.00% |
| Jeremy Fitzhardinge |
3 |
0.43% |
1 |
2.00% |
| Ingo Molnar |
2 |
0.29% |
2 |
4.00% |
| Mario Limonciello |
1 |
0.14% |
1 |
2.00% |
| Maxime Jayat |
1 |
0.14% |
1 |
2.00% |
| Total |
694 |
|
50 |
|
/*
* Routines to identify additional cpu features that are scattered in
* cpuid space.
*/
#include <linux/cpu.h>
#include <asm/memtype.h>
#include <asm/apic.h>
#include <asm/processor.h>
#include "cpu.h"
struct cpuid_bit {
u16 feature;
u8 reg;
u8 bit;
u32 level;
u32 sub_leaf;
};
/*
* Please keep the leaf sorted by cpuid_bit.level for faster search.
* X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID
* levels are different and there is a separate entry for each.
*/
static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
{ X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
{ X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
{ X86_FEATURE_MSR_IMM, CPUID_ECX, 5, 0x00000007, 1 },
{ X86_FEATURE_APX, CPUID_EDX, 21, 0x00000007, 1 },
{ X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 },
{ X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 },
{ X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
{ X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
{ X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
{ X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
{ X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
{ X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 },
{ X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
{ X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
{ X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 },
{ X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 },
{ X86_FEATURE_OVERFLOW_RECOV, CPUID_EBX, 0, 0x80000007, 0 },
{ X86_FEATURE_SUCCOR, CPUID_EBX, 1, 0x80000007, 0 },
{ X86_FEATURE_SMCA, CPUID_EBX, 3, 0x80000007, 0 },
{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
{ X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 },
{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
{ X86_FEATURE_X2AVIC_EXT, CPUID_ECX, 6, 0x8000000a, 0 },
{ X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 },
{ X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
{ X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
{ X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 },
{ X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 },
{ X86_FEATURE_TSA_SQ_NO, CPUID_ECX, 1, 0x80000021, 0 },
{ X86_FEATURE_TSA_L1_NO, CPUID_ECX, 2, 0x80000021, 0 },
{ X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 },
{ X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
{ X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
{ X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 },
{ X86_FEATURE_AMD_HTR_CORES, CPUID_EAX, 30, 0x80000026, 0 },
{ 0, 0, 0, 0, 0 }
};
void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
{
u32 max_level;
u32 regs[4];
const struct cpuid_bit *cb;
for (cb = cpuid_bits; cb->feature; cb++) {
/* Verify that the level is valid */
max_level = cpuid_eax(cb->level & 0xffff0000);
if (max_level < cb->level ||
max_level > (cb->level | 0xffff))
continue;
cpuid_count(cb->level, cb->sub_leaf, ®s[CPUID_EAX],
®s[CPUID_EBX], ®s[CPUID_ECX],
®s[CPUID_EDX]);
if (regs[cb->reg] & (1 << cb->bit))
set_cpu_cap(c, cb->feature);
}
}