Contributors: 16
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Radhakrishna Sripada |
101 |
24.82% |
1 |
2.17% |
| Suraj Kandpal |
87 |
21.38% |
8 |
17.39% |
| Mika Kahola |
48 |
11.79% |
8 |
17.39% |
| Paulo Zanoni |
33 |
8.11% |
3 |
6.52% |
| Dave Airlie |
31 |
7.62% |
2 |
4.35% |
| Lucas De Marchi |
30 |
7.37% |
2 |
4.35% |
| Jani Nikula |
19 |
4.67% |
4 |
8.70% |
| Ville Syrjälä |
14 |
3.44% |
6 |
13.04% |
| Ander Conselvan de Oliveira |
13 |
3.19% |
2 |
4.35% |
| Maarten Lankhorst |
10 |
2.46% |
2 |
4.35% |
| José Roberto de Souza |
6 |
1.47% |
2 |
4.35% |
| Daniel Vetter |
5 |
1.23% |
2 |
4.35% |
| Shashank Sharma |
4 |
0.98% |
1 |
2.17% |
| Chris Wilson |
2 |
0.49% |
1 |
2.17% |
| Imre Deak |
2 |
0.49% |
1 |
2.17% |
| Jouni Högander |
2 |
0.49% |
1 |
2.17% |
| Total |
407 |
|
46 |
|
// SPDX-License-Identifier: MIT
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __INTEL_CX0_PHY_H__
#define __INTEL_CX0_PHY_H__
#include <linux/types.h>
#define MB_WRITE_COMMITTED true
#define MB_WRITE_UNCOMMITTED false
enum icl_port_dpll_id;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_cx0pll_state;
struct intel_display;
struct intel_encoder;
struct intel_hdmi;
void intel_clear_response_ready_flag(struct intel_encoder *encoder,
int lane);
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_cx0pll_state *pll_state);
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_cx0pll_state *pll_state);
void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state);
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
const struct intel_cx0pll_state *b);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
u8 lane_mask, u8 state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
bool intel_cx0_is_hdmi_frl(u32 clock);
u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr);
void intel_cx0_rmw(struct intel_encoder *encoder,
u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed);
void intel_cx0_write(struct intel_encoder *encoder,
u8 lane_mask, u16 addr, u8 data, bool committed);
int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
int command, int lane, u32 *val);
void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane);
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
void intel_cx0_pll_power_save_wa(struct intel_display *display);
void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */